Gigabit Ethernet + FPGA/SoC Bring-Up (Zynq Part 4) - Phil's Lab #99
Gigabit Ethernet PHY (physical layer) and AMD/Xilinx Zynq SoC (System-on-Chip) configuration. Schematic and PCB layout/routing overview, RGMII/MDIO/MDI signals, Vivado and Vitis configuration, fixing driver bugs, example TCP bandwidth performance application, and test.
Chapters:
- 00:00Introduction & Previous Videos
- 02:11Hardware Overview
- 03:36Schematic
- 05:35PCB Layout & Routing
- 06:37Physical Layer (PHY)
- 07:14Vivado Ethernet Set-Up
- 11:10Vitis TCP Performance Server Example
- 12:03Driver Fix #1 - Autonegotiation Off
- 13:02Driver Fix #2 - Link Up/Down Bug
- 16:26Hardware Connection
- 16:42COM Port Set-Up & Programming
- 18:14iPerf Tool
- 18:37Bandwidth Performance Test
- 21:09Summary
- 22:08Outro
