<div class="entry-content">
    <div class="jetpack-video-wrapper"><span class="embed-youtube" style="text-align:center; display: block;"><iframe src="https://www.youtube.com/embed/fFI33f4TejM" class="youtube-player" width="740" height="416.418" frameborder="0" allowfullscreen></iframe></span>
    </div>
    <div class="blog-content">
Ken Burns has published 7 hardware projects on Kickstarter. He explains how it works.
    </div>
    
    <div class="blog-content-links">
        <div>
            Links:
        </div>
        <ul class="links-list">
            <li class="links-list-item"><a href="https://tinycircuits.com/">Ken's company TinyCircuits</a></li>
            <li class="links-list-item"><a href="https://fedevel.com/courses">FEDEVEL Online courses</a></li>
        </ul>
    </div>  
</div>

Can You Make Money on Kickstarter HW Projects?

<div class="entry-content">
    <div class="jetpack-video-wrapper"><span class="embed-youtube" style="text-align:center; display: block;"><iframe src="https://www.youtube.com/embed/2oA4X3OTz0M" class="youtube-player" width="740" height="416.418" frameborder="0" allowfullscreen></iframe></span>
    </div>
    <div class="blog-content">
Interesting experiments and examples to help you to understand ground layout in PCB. Explained by Hans Rosenberg
    </div>


    <div class="blog-content-chapters">
        <div>
            Chapters:
        </div>
        <ul class="chapters-list">
            <li class="chapters-list-item"><span class="chapters-time">00:00</span><span class="chapters-text">What is this video about</span></li>
            <li class="chapters-list-item"><span class="chapters-time">00:19</span><span class="chapters-text">Currents flow under track</span></li>
            <li class="chapters-list-item"><span class="chapters-time">03:10</span><span class="chapters-text">What happen when you are making a board</span></li>
            <li class="chapters-list-item"><span class="chapters-time">08:37</span><span class="chapters-text">Where currents flow</span></li>
            <li class="chapters-list-item"><span class="chapters-time">14:01</span><span class="chapters-text">Experiment: Cut under track</span></li>
            <li class="chapters-list-item"><span class="chapters-time">19:51</span><span class="chapters-text">Floating copper fill</span></li>
            <li class="chapters-list-item"><span class="chapters-time">23:15</span><span class="chapters-text">Grounded copper fill</span></li>
            <li class="chapters-list-item"><span class="chapters-time">27:04</span><span class="chapters-text">Experiment: Filter</span></li>
            <li class="chapters-list-item"><span class="chapters-time">35:05</span><span class="chapters-text">2 Layer vs. 4 Layer</span></li>
            <li class="chapters-list-item"><span class="chapters-time">44:00</span><span class="chapters-text">3 rules to prevent ground problems</span></li>
            <li class="chapters-list-item"><span class="chapters-time">46:05</span><span class="chapters-text">Example: Ground plane</span></li>
            <li class="chapters-list-item"><span class="chapters-time">49:52</span><span class="chapters-text">Example: 1 VIA per GND pin</span></li>
            <li class="chapters-list-item"><span class="chapters-time">54:46</span><span class="chapters-text">Example: Gap in GND plane</span></li>
            <li class="chapters-list-item"><span class="chapters-time">1:02:00</span><span class="chapters-text">Example: FPGA board redesign</span></li>
            <li class="chapters-list-item"><span class="chapters-time">1:05:16</span><span class="chapters-text">Star grounding</span></li>
            <li class="chapters-list-item"><span class="chapters-time">1:07:39</span><span class="chapters-text">Multiple ground planes</span></li>
            <li class="chapters-list-item"><span class="chapters-time">1:14:30</span><span class="chapters-text">Example: Digital and Analog on one board</span></li>
            <li class="chapters-list-item"><span class="chapters-time">1:16:40</span><span class="chapters-text">About Hans</span></li>
    </div>
    
    <div class="blog-content-links">
        <div>
            Links:
        </div>
        <ul class="links-list">
            <li class="links-list-item"><a href="https://www.youtube.com/@HansRosenberg74">Hans´ YouTube</a></li>
            <li class="links-list-item"><a href="https://www.hans-rosenberg.com/">Hans´ website</a></li>
            <li class="links-list-item"><a href="https://fedevel.com/courses">FEDEVEL Online courses</a></li>
        </ul>
    </div>  
</div>

Examples of BAD Ground in PCB Layout And How to Fix It

<div class="entry-content">
    <div class="jetpack-video-wrapper"><span class="embed-youtube" style="text-align:center; display: block;"><iframe src="https://www.youtube.com/embed/X-qubBLJDD8" class="youtube-player" width="740" height="416.418" frameborder="0" allowfullscreen></iframe></span>
    </div>
    <div class="blog-content">
What will happen if you don't have enough GND pins on your connector?
    </div>
    
    <div class="blog-content-links">
        <div>
            Links:
        </div>
        <ul class="links-list">
            <li class="links-list-item"><a href="https://www.colorado.edu/faculty/bogatin/">About Eric</a></li>
            <li class="links-list-item"><a href="https://fedevel.com/courses">FEDEVEL Online courses</a></li>
        </ul>
    </div>  
</div>

Do You Design Connector Pinout Correctly? | Eric Bogatin

<div class="entry-content">
    <div class="jetpack-video-wrapper"><span class="embed-youtube" style="text-align:center; display: block;"><iframe src="https://www.youtube.com/embed/IFLviz722ws" class="youtube-player" width="740" height="416.418" frameborder="0" allowfullscreen></iframe></span>
    </div>

    <div class="blog-content">
        This video tutorial shows how I use micro VIA and  blind VIA in Altium Designer during PCB layout (HDI PCB Technology).
    </div>

    <div class="jetpack-video-wrapper"><span class="embed-youtube" style="text-align:center; display: block;"><iframe src="https://www.youtube.com/embed/OaefGeQrRkA" class="youtube-player" width="740" height="416.418" frameborder="0" allowfullscreen></iframe></span>
    </div>



    <div class="blog-content-text">
       <b><span style="color:#ff0000;">Updated:</span></b> Have a look also on the following video created
            by <a href="http://www.youtube.com/user/elektroniskorg">Elektroniskorg</a>. The video explains how to configure
            Altium Designer Rules for automatic VIA selection during interactive routing. Thank you for a great tutorial.
    </div>

   
    <div class="blog-content-links">
        <div>
            Links:
        </div>
        <ul class="links-list">
            <li class="links-list-item"><a href="http://www.youtube.com/user/elektroniskorg">Elektroniskorg</a></li>
        </ul>
    </div>  
</div>

Altium Designer – Using uVIAs and Buried VIAs in PCB layout

<div class="entry-content">
    <div class="blog-content">
        DDR3 mirroring is a feature of memory controller.<br><br>

        See the following text from <a href="http://www.jedec.org/sites/default/files/docs/4_20_19R20.pdf">DDR3 SDRAM Unbuffered DIMM Design Specification</a> (JEDEC website – Registration is required, page 17).<br><br>

        <i>Following pins are being mirrored: A3<->A4, A5<->A6, A7<->A8, BA0<->BA1.<br><br>

        “Since the cross-wired pins have no secondary functions, there is no problem in normal operation. Any data written is read the same way. There are limitations however. When writing to the internal registers with a “load mode” operation, the specific address is required. This requires the controller to know if the rank is mirrored or not. This requires a few rules. Mirroring is done on 2 rank modules and can only be done on the second rank. There is not a requirement that the second rank be mirrored. There is a bit assignment in the SPD that indicates whether the module has been designed with the mirrored feature or not. See the DDR3 UDIMM SPD specification for these details. The controller must read the SPD and have the capability of de-mirroring the address when accessing the second rank.”</i>
    </div>

    <div class="blog-content-img-wrapper">
        <img src="https://assets.fedevel.com/blog/2019/10/8ea2f-ddr3_mirroring_pcb_layout.jpg" alt="DDR3_mirroring_PCB_layout" />
    </div>

    <div class="blog-content-text">
        To confirm this, have a look on the following pictures from <a href="http://www.jedec.org/sites/default/files/docs/design/DDR3/PC3_12800_UDIMM_V07_RC_B0_20070529.zip">PC3-12800 UDIMM</a> layout where I have selected A8 signal:
    </div>
    <div class="blog-content-img-wrapper">
        <img src="https://assets.fedevel.com/blog/2019/10/b9f76-ddr3_mirroring_top_and_bottom_layout.jpg" alt="DDR3_mirroring_top_and_bottom_layout" />
    </div>
    
    <div class="blog-content-text">
        <i>Details of A8 Top and Bottom Layer:</i>
    </div>
    <div class="blog-content-img-wrapper">
        <img src="https://assets.fedevel.com/blog/2019/10/b37e2-ddr3_mirroring_top_layout1.jpg" alt="DDR3_mirroring_top_layout" />
    </div>
    <div class="blog-content-img-wrapper">
        <img src="https://assets.fedevel.com/blog/2019/10/47294-ddr3_mirroring_bottom_layout.jpg" alt="DDR3_mirroring_bottom_layout" />
    </div>
    
    <div class="blog-content-text">
        <i>Screenshot from schematic for D1 and D9:</i>
    </div>
    <div class="blog-content-img-wrapper">
        <img src="https://assets.fedevel.com/blog/2019/10/9bb0b-ddr3_mirroring_schematic.jpg" alt="DDR3_mirroring_schematic" />
    </div>


    <div class="blog-content-text">
        Components D1 and D9 are listed in the BOM with same part number.
    </div>

   
    <div class="blog-content-links">
        <div>
            Links:
        </div>
        <ul class="links-list">
            <li class="links-list-item"><a href="http://www.jedec.org/sites/default/files/docs/4_20_19R20.pdf">DDR3 SDRAM Unbuffered DIMM Design Specification</a></li>
            <li class="links-list-item"><a href="http://www.jedec.org/sites/default/files/docs/design/DDR3/PC3_12800_UDIMM_V07_RC_B0_20070529.zip">PC3-12800 UDIMM</a></li>
        </ul>
    </div>  
</div>

DDR3 memory mirroring – PCB layout

<div class="entry-content">
    <div class="blog-content">
        The best high speed design tutorial for PCB layout in Altium Designer what I have found. It’s worth to have a look.<br><br>

        <i><b>High-Speed Digital Board Design with Altium Designer</b> by Istvan Nagy, Electronics Design Engineer, Blue Chip Technology. (<a href="https://assets.fedevel.com/blog/downloads/HiSpeedDesignTutorialforAltiumDesigner.pdf" target="_blank">download pdf here</a>)<br><br>

        Picture: A page from the tutorial</i>
    </div>

    <div class="blog-content-img-wrapper">
        <img src="https://assets.fedevel.com/blog/2019/10/0c528-altium_designer_high_speed_tutorial.jpg" alt="altium_designer_high_speed_tutorial" />
    </div>

   
    <div class="blog-content-links">
        <div>
            Links:
        </div>
        <ul class="links-list">
            <li class="links-list-item"><a href="https://assets.fedevel.com/blog/downloads/HiSpeedDesignTutorialforAltiumDesigner.pdf" target="_blank">High-Speed Digital Board Design with Altium Designer - PDF file</a></li>
        </ul>
    </div>  
</div>

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