FEDEVEL
Platform forum

Mihai , 04-13-2019, 01:14 PM

Hi,

Is there a rule or standard on how much should be the clearance between the vias of a differential pair which is passing from top to the bottom layer? e.g. is correct to have the vias as the way are in the attached image? Or I have to define a specific clearance rule just for this problem?

Cheers,
Mihai

Lakshmi , 04-14-2019, 02:12 AM

That should be okay.

Mihai , 04-14-2019, 06:12 AM

thanks Lakshmi.
Also I have a question and maybe @robertferanec can answer to it or others. How do you set the rule for differential pairs to be length matched on each layer they travel? On Altium 18, I see that is given the whole length on all layers, how can I imply a separation and to ensure length matching on every layer?

Cheers,
Mihai

Lakshmi , 04-15-2019, 01:12 AM

From the Manufacturing team you'll get the 90 Ohm impedance trace width and separation and add that.
idk how do you do this in Altium (I haven't used yet) since i work in KiCAD.

Mihai , 04-15-2019, 01:17 AM

Hi @Lakshmi I am not referring on how to route the differential pairs with a given impedance, I am referring on how to keep the same length of the pair on each layer where is routed. Especially if there a rule for that, other than just measuring the selected object on a given layer.

Cheers,
Mihai

robertferanec , 04-18-2019, 02:33 AM

We do this in Altium manually. I am not sure if there is a straight forward rule to check this.

About the VIA space - I normally use the same clearance as is set for the differential pair.