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DDR3 Timing Budget
Raza Parvi , 09-02-2019, 03:00 AM
Hello Everyone, I have been working on a board with DDR3 RAM and so far unable to comprehend the Timing budget portion properly. I am confused in trace length relationship with frequency/Time. eg: How a minimum tolerance of a data group trace length is set while seeing the max clock frequency of the RAM.Any one please suggest me few sources where these topics are practically illustrated through some easy examples. Thanks.
robertferanec , 09-03-2019, 08:09 AM
There may be differences between processors in DDR3 layout requirements (routing topology, length matching requirements, etc). So the best is to try to find specific datasheet / design guide / application note / reference design for your CPU.
Generally, maybe this can help (picture below is for T-Branch but you will get an idea what is also important for Fly-By topology). Those rules are based on iMX6 Design guide (you can find there more info): http://cache.freescale.com/files/32b...6DQ6SDLHDG.pdf
If you would like to know more about Fly-By, maybe have a look here: https://www.fedevel.com/welldoneblog...useful-things/
Generally, maybe this can help (picture below is for T-Branch but you will get an idea what is also important for Fly-By topology). Those rules are based on iMX6 Design guide (you can find there more info): http://cache.freescale.com/files/32b...6DQ6SDLHDG.pdf
If you would like to know more about Fly-By, maybe have a look here: https://www.fedevel.com/welldoneblog...useful-things/
Raza Parvi , 09-19-2019, 04:55 AM
Thanks Robert.
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