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AntiPad in Altium

Lakshamana Balakrishnan , 11-16-2021, 11:00 PM
In Allegro, we have Antipad for pad clearance, In alitum where do we find that similar thing? Kindly explain your suggestions?
qdrives , 11-17-2021, 04:40 PM
Do the clearance rules not do what you want?
Design / Rules. Design rules / Electrical / Clearance.
Antipad would be like the clearance for via and TH pad, but I do not know what Allegro has/does.

Lakshamana Balakrishnan , 11-17-2021, 09:30 PM
yes @qdrives by clearance rule we can control everything. But i just curious to know any similar primitives like anti-pad.
qdrives , 11-18-2021, 02:49 PM
From the little I can see from images in google search, I would say Altium does not have that. You just define it all though the rules.
Lakshamana Balakrishnan , 11-19-2021, 12:31 AM
@qdrives Thanks for the support
JohnsonMiller , 06-07-2023, 06:58 AM
On multilayer boards with high-speed differential lines, which are common these days, it is quite sad and heartbreaking that Altium does not offer anti-pad! I have done a lot of simulations, without anti-pad no way for over 1Gbps rates!
Hope Altium engineers are looking at forums like Fedevel and take the issue seriously, let's keep our fingers crossed.

But on the other hand, I was thinking that we can set a series of rules and implement it by ourselves, since I am not good at setting rules need your help. Steps like this:
- if the pad belongs to diff-pair
- add a square shape set back for each plane
I do not know which command or rules can set void or setback in the planes, any help?
qdrives , 06-07-2023, 03:06 PM
The rules are quite simple.
My first question to you would be if the clearance (yes, anti-pad is like a clearance) only should be applied to THpads/vias or also for traces?

In you question aboce @JohnsonMiller, you state "if the pad belongs to diff-pair" should be changed to (IsPad Or IsVia) and InNetClass("HighSpeed") for example.

I have little experience with differential pairs, but I do think that you would like the clearance to other nets (including Gnd) but not towards the other of the pair.
That is why I show the "Different Differential Pair" option in the screenshot above. However, Gnd is not a differential pair, so I do not know if that works.
The easy way to check if it work is to set an overly large clearance (lets say 1mm) and see if/where it fails.

Just ask again if you cannot get it to work, but please do show then what you have defined.
JohnsonMiller , 06-08-2023, 01:48 AM
@qdrives, the anti-pad is similar to clearance but the shape is different, the anti-pad is not uniform around the pad
another point, it applies to the plane o​r polygon, and the plane is not listed in the clearance items

In the stack-up setup we can define a plane layer as a reference for the signal layer, is there any command to detect the reference layers?
qdrives , 06-08-2023, 02:38 PM
Why would you want the anti-pad to be a different shape? Do note, I am not a high speed designer, so please enlighten me.

Anyhow, for consistency (ahum)

is there any command to detect the reference layers?
Something like: You mean that you want the clearance to the reference layer to be smaller than other plane layers?
Yes, and no. Not something automatically, but you could use net classes and then set clearance rules for those classes to specific layers.
JohnsonMiller , 06-09-2023, 04:19 AM
The anti-pad is not a simple clearance issue, this image may help

JohnsonMiller , 06-09-2023, 04:30 AM
I found this image from Zuken even more helpful:
In the Altium case, we have to add anti-pad manually, but with a complex board it is very difficult, I was thinking of creating a script or setting rules to implement it.
qdrives , 06-09-2023, 04:52 PM
Interesting. However, I do think that it may be partly a bit more complicated and for another part more easy.

But first of all, from the little experience I have with planes, this would not be possible in the current version of Altium by using planes. With polygon pours it might be possible.

Let me hear your thoughts on this:
The 'rectangle' is there to give the feeding trace a return plane as much as possible. The 'clearance' from the via is to reduce the capacitive coupling to the other layers.
Below is just for a single (ended) signal.

The anti pad on reference layer.
In 3D

I created the shape of the polygon pour cutout in FreeCad. Exported this in DXF and imported into Altium.
Took only the 'anti-pad' converted it to a (polygon pour) cutout. Change the layer to the correct layer and move it to the via.


For all other layers (not a reference layer) you just want a bigger clearance and remove/reduce the copper between the vias.

For all this you do not need a complex script. Just a FreeCad drawing that can easily modified to the via size you use. Afterwards it is just a question of copy/paste to the correct locations. For that, a script may be used
JohnsonMiller , 06-18-2023, 02:49 AM
@qdrives, thank you for your detailed and helpful explanation
The problem with my design is that I have many locations which need anti-pads, adding them manually if not impossible is very difficult, may take days.

BTW- I guess you agree with me that Altium engineers should act and add anti-pad feature to AD.
qdrives , 06-19-2023, 01:07 PM
I can imagine that creating a 'component' for it would be faster to use in layout.

BTW- I guess you agree with me that Altium engineers should act and add anti-pad feature to AD.​
Actually no. I do not do high speed and for me there would be many more things that I would like to change/add to AD.
But, I can image that it would be very helpful for you and other high speed designers.


Another set of questions for you:
- Is my assumption correct that the "bump" is there to extend the reference layer for the trace?
- What about reference via's?
- Do you know if this is the best structure? I.e. have you done simulations and/or measurements?
JohnsonMiller , 06-19-2023, 01:37 PM
@qdrives, regarding your questions, I am not expert in this field just practicing, BTW.
"- Is my assumption correct that the "bump" is there to extend the reference layer for the trace?"
- Yes, those little extensions are to keep impedance continuity as far as possible

"- What about reference via's?"
- The reference via is another option if PCB has enough space, in my case those are PADs not via and PCB is very packed and tick, so no space for extra via, otherwise production price can increase.

"- Do you know if this is the best structure? I.e. have you done simulations and/or measurements?​"
- I am not sure, but I have done a lot of modeling and SI simulation, without an anti-pad I am sure no way! design will fail!
qdrives , 06-20-2023, 04:16 PM
Then also let me put it in a question:
Would it be helpful if you made a 'component' that has it all?
Do other tools place the anti-pad structure automatically when you change layers (place a via)?

Length matching would then be from IC to via, via to via and via to IC.
You'd also need to place the 'components' in the schematic.

Alternatively, you create the advanced anti-pad once and paste it everywhere you need after you 'finished' routing.
JohnsonMiller , 06-22-2023, 12:38 AM
To the best of my knowledge!

"Would it be helpful if you made a 'component' that has it all?"
- I am afraid, NO! Since at the component level, we do not have the option to shape the plane layer, and anti-pad is mostly related to planes.

"Do other tools place the anti-pad structure automatically when you change layers (place a via)?​:"
- For Allegro and Zuken, I am sure that they both add anti-pad automatically, but PADS and Expedition, not sure!

"Length matching would then be from IC to via, via to via, and via to IC."
- Yes, anti-pad usually does not affect length matching

"You'd also need to place the 'components' in the schematic.​"
- No, anti pad has nothing to do with the schematics

"Alternatively, you create the advanced anti-pad once and paste it everywhere you need after you 'finished' routing.​"
- Yes, this is the final solution if we can not find an automatic approach.
qdrives , 06-22-2023, 02:15 PM
Did you create an "idea's" item at Altium?
If I search "anti" there (https://bugcrunch.live.altium.com/#/...i&CategoryID=0 ), I do not get anything like anti-pad.
Asking here does not notify Altium.


More links, but no extension for the reference plane...
You are a backplane designer and have been assigned to engineer a  new high-speed, multi-gigabit serial link architecture from several line cards to multiple fabric switch cards across a backplane.…

Via stub accumulate loss for high speed and high frequency signals. Here’s how you can spot problems with stubs and solve them easily.


High speed PCBs and RF PCBs often need to make via transitions that carry signals between layers. We’ll look at how to design these transitions in this article.



If I read here https://www.zuken.com/en/blog/top-5-...gn-force-2021/ I do not have a feeling that Zuken places the 'complex' antipad automatically.
qdrives , 06-25-2023, 02:22 PM
Something like this...
But it does not work with planes, just copper pours.
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