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About vias that do not connect with internal layer
mulfycrowh , 08-17-2022, 05:31 AM
Hi everyone,
I have a few vias located on a vertical line, connected to a polygon pour on the top layer.
The net name for those vias is 3V0_S0.
I have an internal layer embedding a large polygon pour with same net name.
The vias do not connect on this internal layer.
Some of them trigger an antennae violation, the other ones don't.
Any idea maybe ?
Thanks a lot.
I have a few vias located on a vertical line, connected to a polygon pour on the top layer.
The net name for those vias is 3V0_S0.
I have an internal layer embedding a large polygon pour with same net name.
The vias do not connect on this internal layer.
Some of them trigger an antennae violation, the other ones don't.
Any idea maybe ?
Thanks a lot.
mulfycrowh , 08-17-2022, 08:13 AM
Guys, I found the issue.
It was written in the screenshot: I wrote 3V0_S0 instead 3V3_S0 on power supplies.
It is worth one dislike !
It was written in the screenshot: I wrote 3V0_S0 instead 3V3_S0 on power supplies.
It is worth one dislike !
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