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ican7 , 09-11-2015, 06:23 AM

Hi Robert, I keep getting Net antenna warning on DRC.What is it? and how can I resolve it?

robertferanec , 09-11-2015, 06:25 AM

@ican7, just delete the small piece of track which is marked as antenna.

robertferanec , 09-11-2015, 06:37 AM

Is not that a different DRC? Go to your PCB, go to the right bottom corner and press "PCB" button. Then select "Rules and Violations". Browse through the violations, double click on it, press "JUMP" and "HIGHLIGHT" to identify the exact place of the DRC. Possibly, please attach a screenshot with "Rules and Violations" window + your PCB with DRC.

ican7 , 09-11-2015, 06:50 AM

please find the screenshot Robert.

ican7 , 09-11-2015, 06:59 AM

please find the pcb.

robertferanec , 09-11-2015, 07:01 AM

It looks to me like the VIAs have no Net Name. Double click on the VIA and check. You probably want to set Net Name to "GND".

ican7 , 09-11-2015, 07:07 AM

They all have net name and connected to gnd net.

ican7 , 09-11-2015, 07:12 AM

yes both top and bottom as well as the middle layers.

robertferanec , 09-11-2015, 07:20 AM

I would have to see your PCB, but I would expect getting this kind of error when VIA is connected on 1 layer only. Double check if all your polygons have Net Name assigned. I am sure you can figure it out. Please let me know then what the problem was.

BTW: try to check "Remove Dead Copper" when you double click on the GND polygon pour.

ican7 , 09-11-2015, 07:28 AM

For some reason when I redone the DRC the net antenna issue dissappeared. I didn't do nothing but it comes back on and off... Would it be a bug in Altium?

robertferanec , 09-11-2015, 07:31 AM

Fantastic! I do not really know if it's a bug in Altium (we normally dont have this kind of problems), important is, it's now ok

Naveen-Krishnan , 07-06-2018, 05:59 AM

Hi,

I got the same Net Antenae violation on Vias. But fortunately I was able to find a solution. Here it goes

Firstly, I added shielding vias surrounding a RF trace. The vias was given GND net. At this time I had the following stackup
1. TOP
2. GND
3. IN1
4. IN2
5.PWR
6. BOT

There was only 1 ground plane dedicated to my PCB. At this time I thought of disregarding the violations thinking that its a bug in Altium.

Secondly, during layout review my colleague told me add GND copper pours in the Inner layers to get Stripline trace and better impedance. Suddenly the NET Antenae via violation went away.

I was because of insufficient GND planes in the PCB, Altium was showing Net Antenae violation (according to my case).

Hope it helps someone.

Cheers ! Bye.

robertferanec , 07-10-2018, 05:37 AM

Yes, that is expected behavior. In second example the VIAs were making connections between the two planes. In the first example, the VIAs were not doing any connections.

Naveen-Krishnan , 07-10-2018, 09:03 AM

Yes Robert Feranec. Thanks for your reply.