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marcos , 09-06-2016, 08:21 PM

Hi Robert,

I'm glad to join your discussion here on Altium and PCB design and would love to get some input from you on my threads.

Below is a copy of the message I sent to you initially with my question about SI in Altium Designer.
Right now, I have a question regarding SI in Altium 14. Since I read a lot of material and have seen a whole lot of videos about the subject, Signal Integrity and High Speed Designs, I decided not to proceed any further with my PCB project unless everything for SI was taken into consideration. The board is a flash card based on 8x 2GBit Parallel NOR Flash. Aside from passive components, it has only the connector, VHC139 - 2 to 4 address decoder, and the NOR Flash ICs.

As usual, I started from the schematic level by setting all the models for SI and I have the IBIS model for the NOR Flash already. At the beginning, I was able to see most nets analyzed and passed to the SI tool with bunch of others still not screened/analyzed. Now, I just can't figure out what I did so most nets are no longer being analyzed with the majority of them showing "Not Analyzed" and only those associated with the decoder chip passed the test successfully. I was wondering if Net Classes, or any other schematic directives had anything to do with the SI test.

I would really appreciate any input from you!

Thank you again for your kindness and excellent support!

marcos , 09-06-2016, 08:40 PM

Dear Robert,

In addition to my first concern about SI, I have some questions about other areas that concerns the design itself.

Well, the first thing is application note or guidelines when designing with Parallel NOR Flash. Research has revealed only couple of notes from MicronTechnology and both of them were of little help. I did not find much about tolerances (or maximum net length mismatch) between signals of certain group, how to route each group and the best routing topology for each, and many other details that you used to find in other design guidelines for DDR and SDRAM chips. So, basically, do you have any advice or a rule of thump to follow when working with Parallel NOR Flash chips?

For matching the impedance, which I believe is a requirement for such a design, I initially had hard time getting the right impedance with traces of < 6 mil, however, thanks to your 6-layer Advanced Stackup, which has solved all the issue and now I can achieve 5.85 mil with a 55 Ohm line impedance. I don't know if that's all as far as impedance control is concerned.


Regarding my first question about SI, I would like to mention here that all DQ signals are interrupted with a series resistor between the source pad in the connector and the final destination pad on the memory chip. In such a situation, how would you deal with distribution of address, control, and data lines for 4 chips, two of them are on top and the other two are on the bottom side of the PCB? What is the best topology to be used here? And how to do signal analysis?

Thank you again, and I look forward to hearing from you soon!

Marcos

robertferanec , 09-08-2016, 05:19 PM

Hi @marcos. With NOR you should be fine. Use a good stackup to minimise crosstalk between tracks and meet impedance. It may not be necessary, but you may want to do some kind of length matching, e.g. you may want to make data signals similar lengt, strobe signals a little bit longer then the longest data. Be sure, the data are correctly routed also on the board where this flash card is inserted. Be sure, the delay in address decoder will not influence your timing.

If you attached some screenshots from your simulations and what is wrong, that would help.

Impedance and track width will depend on your stackup. Be sure you get the track geometry from your PCB manufacturer or you can re-use some of our stackups: Download PCB Stackups – Free for your Projects

For more chips used in parallel I would go for Balanced T-Branch topology:
...............................--------CHIP 1
.......................------<
......................| .......--------CHIP 2
Connector -----<
......................| .......--------CHIP 3
.......................------<
...............................--------CHIP 4

I normally do not simulate this kind of connections, but if you are not sure, you can try at least reflection and crosstalk. Just send a pulse from the source (output pin) and see how it looks in destination (input pin(s)). Do it for different scenarios - e.g. read, write - when in one situation a pin can be output and in different situation the pin can be input.

BTW: I do not simulate in Altium as I am not convinced about results from the Altium simulator, but maybe I will see something unusual.