FEDEVEL
Platform forum

sneha.xeye , 12-10-2017, 10:15 PM

Hello,
i recently designed a circuit using through hole vias for the first time but got reply form the manufacturer as attached in an image below..
so is that create a problem in circuit connectivity or its normal to keep it as same? (i have set the solder mask expansion value to zero in vias.)

robertferanec , 12-12-2017, 09:56 AM

Hello, please, could you try to attach the picture again? I can not see it in the post.

sneha.xeye , 12-12-2017, 09:33 PM

observation attachment @robertferanec

robertferanec , 12-13-2017, 09:25 AM

if that is what you were planning, just tell them it is fine.

PS: I believe, what they are saying is, that you unmasked the hole of these VIAs and the mask is smaller than VIA diameter. Their software probably noticed "unusual" mask (smaller than pad) and therefore they need your confirmation if that is ok. Possibly double check these four VIAs ... what is unusual on them (maybe you copied them from different design)?

sneha.xeye , 12-14-2017, 12:20 AM

@robertferanec i haven't copied it.. i just set mask expansion to zero.. is that create a problem in internal via connections? I mean is it same to tent a via or keep mask opening to zero??

robertferanec , 12-15-2017, 12:24 PM

If you would like to cover the VIAs, you may want to check "tenting" or you need to use negative expansion. If expansion is 0, it means it has same size as the pad. If you use a positive expansion number, it means how much bigger the mask opening is comparing to the pad ... if you use negative expansion number, it means how much smaller the mask opening is comparing to the pad edges.

PS: Mask settings are not influencing electrical connection of VIA.

Notice the "Force complete tenting on top/bottom":

sneha.xeye , 12-15-2017, 09:22 PM

Thank u so much @robertferanec