FEDEVEL
Platform forum

SoroushPCB , 07-16-2018, 12:45 PM

Hello all,

May I ask if there is a way to check the LVS on the PCB just like how we do it for a cadence layout and schematic?

Thanks,
Soroush

robertferanec , 07-18-2018, 08:45 AM

What do you mean by LVS?

SoroushPCB , 07-18-2018, 11:09 AM

Layout versus schematic (LVS) is something that shows if all the connections are done and there is no missing connection. In cadence, we have to check DRC and LVS to ensure if all the nodes are connected to each other and also there is no violation according to the drawing rules.

mairomaster , 07-19-2018, 02:10 AM

In Atlium when you import changes from schematics it creates an ECO where you can see all the differences and chose which to import. Doing the DRC tells you if everything is fine in the layout based on the imported information from the schematics and the PCB rules.