Benjamin36 , 11-08-2025, 02:34 PM
Hello, I’m currently working on Phil’s Advanced Digital Hardware Design course and have started tuning the delay of the ACC signals in DDR3. I’ve already defined the package delay for each pin on the SoC side, but I’m not sure what values to use for the DDR3 chip’s package delay.I came across a post where Robert mentioned that delay tuning is already handled in the packaging, but can anyone confirm this? Should I keep the DDR3 pin delay at 0 ps, or is it better to assign around 20 ps per each pin?