, 06-23-2026, 10:03 AM
🤖 In the meantime, here’s a response from the [FEDEVEL AI HW Assistant]().It helps to find relevant resources for your question, but it may make mistakes as it’s still in early development.This is the response from the AI Assistant:From the video content available, room violations in PCB design typically occur due to component-to-room assignment mismatches or rule configuration issues. Here are the key technical reasons based on the material:1. **Component Class Mismatch** Rooms are often associated with component classes defined in the schematic. If components aren't properly assigned to these classes (either through schematic directives like blankets or explicit class parameters), they won't be recognized as belonging to the room. This creates violations when components are placed outside their designated areas. *Source*: [Component class association in project options](https://www.youtube.com/watch?v=aXjcSAsHkRQ&t=3190)2. **Incomplete Room Definition** Rooms require explicit boundary definitions. If the room outline doesn't fully enclose its assigned components (or contains extra space), Altium may flag placement violations. This often happens when rooms are modified after initial placement without updating component associations. *Source*: [Room boundary and component containment](https://www.youtube.com/watch?v=aXjcSAsHkRQ&t=3190)3. **Rule Inheritance Conflicts** Rooms can have specific design rules (clearance, routing, etc.) that override global rules. If components within a room violate these localized rules while complying with global ones, you'll get room-specific violations. Check nested rule priorities in Design > Rules. *Source*: [Rule hierarchy demonstration](https://www.youtube.com/watch?v=f7GP6NZs0Ok&t=2062)4.