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Hi speed signals: RPI Carrier boarad with MIPI DSI, GbE, HDMI, PCIe
hitech95 , 04-10-2021, 03:01 PM
Hi,
I'm working on a my own carrier board for th RPI Compute module (CM4). I'm interested on routing some of its busses to some connectors.
I'm working with Altium and this is the initial layout I was thinking about, is there something obviusly wrong?
Any suggestion would be awesome. All I've learnt so far is from the awesome content created by Robert! Right now I'm also usign the documentation from TORADEX and SMARC to better understand thoosemore advanced stuff.
I know that I should length match each single segment but I have no idea on how I should do it. Also I have the offset of the signal in the SOM but I have no idea on how I should keep that into consideration when I try to length match the singnals.
For what I can understand the most critical bus is the MIPI DSI one. The only strictly required bus is the PCIE and Ethernet one. (it must work no exception)
PCIe is a bit more flexible. and Ethernet and USB seems to be the most flexible ones.
I'm tring to do my best by making the board chapely to manufacture (couple of dollar) by some china PCB prototype service.
On the image above you can see the PCIe bus (green), the MIPI (orange) and the HDMI (blue).
The HDMI is in routed on TOP layer while the others is mostly routed on the bottom layer. (As you see I've put also vias for ground return current)
The SOM is on top layer, the MIPI connector is on bottom layer, the HDMI, RJ45, NGFF Type 2 are all on top layer.
The white one the USB 2.0 one. Is also a lot easier to route.
This is my STACKUP: TOP, BOTTOM is signal, MID LAYER 2 IS generally a GROUND or POWER PLANE but due to some constraint on other PCB area I had to route some low speed singnal on it. (Unfortunalty on a section of the board I have to use both TOP and BOTTOM layer to route Horizontal signals due to space and impedance contraints)
This is my rules in my stackup for impedance matching:
Any help or suggestion is welcome, I'm a noob on this stuff, I'm more an software engeneer than a electronic one, this is done on my spare time for fine during lockdown to keep me busy!
Robert thanks again for all your free resources available, I've learnt so much!
Have a nice day,
Nicolò
I'm working on a my own carrier board for th RPI Compute module (CM4). I'm interested on routing some of its busses to some connectors.
I'm working with Altium and this is the initial layout I was thinking about, is there something obviusly wrong?
Any suggestion would be awesome. All I've learnt so far is from the awesome content created by Robert! Right now I'm also usign the documentation from TORADEX and SMARC to better understand thoosemore advanced stuff.
I know that I should length match each single segment but I have no idea on how I should do it. Also I have the offset of the signal in the SOM but I have no idea on how I should keep that into consideration when I try to length match the singnals.
For what I can understand the most critical bus is the MIPI DSI one. The only strictly required bus is the PCIE and Ethernet one. (it must work no exception)
PCIe is a bit more flexible. and Ethernet and USB seems to be the most flexible ones.
I'm tring to do my best by making the board chapely to manufacture (couple of dollar) by some china PCB prototype service.
On the image above you can see the PCIe bus (green), the MIPI (orange) and the HDMI (blue).
The HDMI is in routed on TOP layer while the others is mostly routed on the bottom layer. (As you see I've put also vias for ground return current)
The SOM is on top layer, the MIPI connector is on bottom layer, the HDMI, RJ45, NGFF Type 2 are all on top layer.
The white one the USB 2.0 one. Is also a lot easier to route.
This is my STACKUP: TOP, BOTTOM is signal, MID LAYER 2 IS generally a GROUND or POWER PLANE but due to some constraint on other PCB area I had to route some low speed singnal on it. (Unfortunalty on a section of the board I have to use both TOP and BOTTOM layer to route Horizontal signals due to space and impedance contraints)
This is my rules in my stackup for impedance matching:
Any help or suggestion is welcome, I'm a noob on this stuff, I'm more an software engeneer than a electronic one, this is done on my spare time for fine during lockdown to keep me busy!
Robert thanks again for all your free resources available, I've learnt so much!
Have a nice day,
Nicolò
Lakshmi , 04-12-2021, 12:13 AM
Hi Nicolo,
You can go through the datasheet of PI CM4 for high-speed layout design guidelines also look for few resources.
Few are:
a)https://cutiepi.io/#:~:text=CutiePi%...July%2C%202021.
b)https://github.com/QWaveSystems/QWAV...Altium-Library
The layout of the diff pair looks ok but widen the gap between MIPI (orange) pairs.
Yes, you can get it manufactured for a cheap price in JLC/PCBway. But what's the board dimension?
Thanks.
You can go through the datasheet of PI CM4 for high-speed layout design guidelines also look for few resources.
Few are:
a)https://cutiepi.io/#:~:text=CutiePi%...July%2C%202021.
b)https://github.com/QWaveSystems/QWAV...Altium-Library
The layout of the diff pair looks ok but widen the gap between MIPI (orange) pairs.
Yes, you can get it manufactured for a cheap price in JLC/PCBway. But what's the board dimension?
Thanks.
robertferanec , 04-12-2021, 04:55 AM
I would maybe swap the PCIE the way like this?
hitech95 , 04-12-2021, 05:18 AM
I didnt want to specify a PCB manufaturer for advertisement but yes the board is bigger than the standard 10x10 so I'll pay more it is also a 4 Layer one.
I'm in fact using the Qwave library with some fixes on the sch symbols. They were not aligned to my grids (for schematic I use the standard 100mils)
I did some cleanup during the weekend, minimal space between MIPI pairs is around 13/14mils ( I have to find a way to properly set between pair clearance):
I used this trick to properly route the signals to the NGFF connector. I know that I could swap P and N signals (I also asked confimation to the RPI guys about that), so you would do a vertical route on top later that horizontal on bottom and back on top the other side of the connector.
Thoose PCIe connectors are not PCIe thoose are just used to power and provide signals (i2c and i2s) to daughterboards.
I'm in fact using the Qwave library with some fixes on the sch symbols. They were not aligned to my grids (for schematic I use the standard 100mils)
I did some cleanup during the weekend, minimal space between MIPI pairs is around 13/14mils ( I have to find a way to properly set between pair clearance):
I used this trick to properly route the signals to the NGFF connector. I know that I could swap P and N signals (I also asked confimation to the RPI guys about that), so you would do a vertical route on top later that horizontal on bottom and back on top the other side of the connector.
Thoose PCIe connectors are not PCIe thoose are just used to power and provide signals (i2c and i2s) to daughterboards.
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