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zeino , 02-09-2016, 05:50 AM

Is Top overlay layer (Yellow Line) same as courtyard space of the component? It seems they are different. How would we know how close the components can be to each other specially with SO8's or the ISIL chip. We don't show with the mask the necessary distance clearance to chip anywhere do we?

robertferanec , 02-10-2016, 12:06 AM

In our designs, we usually draw the Top overlay as the biggest size of the component - so you are sure if you place two components close to each other with touching Overlay, it will be possible to fit them. In assembly layer, we draw a simple shape around the component, but we do not use this layer as the component courtyard - it's just to show component location.

EVW13 , 02-16-2016, 11:27 AM

Hi zeino,

Component courtyard is completely not equal to silkscreen outline- generally silkscreen is atavism from 70x years when PCBs were manual assembly was the mainstream. If you take a look at any modern PCB, specially HDI with tight placement you will see there is no any silkscreen outline and no polarity marks- because it's not required for any modern automated assembly.

At the same time tight courtyard is extremely important footprint detail as it defines the minimum distance between components- least distance is courtyard edge to edge.

mairomaster , 02-17-2016, 01:49 AM

Overall I agree with EVW13's opinion. However, I think that some silk screen information can be quite useful during debugging of a board. That would most often be reference designators (usually only with bigger components due to the lack of space for all of them), test point labels and other useful visual information.

It is true that the idea of the courtyard is to allow the densest placement of components without problems during the assembly. I depends on the software you are using though, if you will be able to use the courtyard properly. Altium Designer for example doesn't have a default rule which accounts for courtyard clearance. I haven't found an easy way to set one up as well. And without a rule, you can use the courtyard for visual inspection and assembly information only. It is a different story of course that Altium has a different mechanism of checking components clearance, but this goes into an off-topic.

EVW13 , 02-17-2016, 02:34 AM

Yes, in some cases silkscreen may serve good job for better visual recognition- but far in not all cases it can be implemented, and what is more important- needed to be implemented: if one has for example testbench with pogo pins and other stuff if it's not required, if one is soldering wires to each TP thinking like”Hmmm, and what was that TP?” of course it's better to have some board level info.

zeino , 02-17-2016, 08:55 AM

Thank you guys for your insight on this. I think in the Video and the way footprint is being made there is a mixture which is not 100% logical. At one hand on the overlay we abide by the IPC rules of courtyard in depicting the overlay for chip cap and resistors and the other hand we don't do that for the IC's so there isn't the consistency on what we are trying to do and that raises the question asked here: "What is the overlay for?" I agree with what you say about overlay on previous posts ("EVW13, Mairomaster") . It is just an indicator for the component and that is it. On the other hand courtyard and manufacturing courtyard (as you said) are assembly indicators and are of mechanical nature and has to be treated that way in my opinion.

In footprint we don't need to shape the courtyard on the overlay (we may even go with component outline+pads) but if we want to abide by the IPC rules in our design we need to define a courtyard and component outline as Altium suggests in our footprints as extra layers. I believe Altium IPC compliant footprint generator does that but I still have to learn it.

Based on what I saw so far from Altium, if in our footprints we do have different layers for courtyard and component outline we should be able to put rules for them on the placing and that would fulfill the purpose of courtyard but that is so much extra work for building the footprint for that purpose by hand. I think that is why they built the IPC compliant tool. FP wizard puts courtyard on layer 15 and outline on layer 13. Logically for each layer one should be able to define rules accordingly.

Still if making the footprint myself I will restrict the overlay to component outline+pads (like what EVW13 has in his picture). Based on IPC standard one can add constant value to (component outline+pads) to make sure it abides by one of 3 levels of IPC clearances, if one doesn't have the courtyard defined in its footprint layers. That means, the overlay will be around the nominal pad positions and then I would put rule on it for the courtyard access of 0.25mm. I think it should be possible to tell Altium to abide by that clearance values form the (component outline +pads) but I still have to learn how. From IPC stand point the pads position and size differ on what class you are using but if I follow that rule without the IPC footprint all footprints I build without the FP wizard would be consistent with the nominal value.

I think EVW13 on his last post is showing the same concept but I didn't understand the 0 clearance thing. It seems based on your experience putting rules on the layers when placing is not as easy as I think it should be. I need to experience that and learn more about it.

EVW13 , 02-17-2016, 10:08 AM

Meaning Altium I can say with confidence that its footprint calculator has nothing with IPC-7351 standard: as maximum it looks like it has some own “understanding” of it with pretty specific values as result. On attached pic you can see difference between Altium calculator and true- IPC compliant one:



What about assembly issues- most probably you saw pic like that in many PCB designs:




Which shows how often people underestimate the value of nice courtyards- because the right case is below.

This particular issue is coexisting very often with its “best friends”- mix of different land patterns(least, nominal, most) and badly though-out copied footprints from really wired libraries. Resuming all above- better not believe to anyone and always do own libraries.

What about courtyard definition- you can select any mechanical layer for it, and in library it's only required to define it on single layer. In target design you should use mechanical pairs then- and meaning “zero clearance rule from previous post” it's possible to rephrase it like this: courtyard line has width which matters, so imagine you want to place couple resistors like on pic above- to perform you use that rule, switch on mechanical snaps on mech layers, select footprint's vertex in courtyard area and just move to other vertex and thus place parts edge-to-edge.

robertferanec , 02-17-2016, 10:26 AM

@EVW13 very nice pictures!

What IPC calculator do you use / recommend?

EVW13 , 02-17-2016, 10:34 AM

This one. But only calculator, without .STEP output- there is no such footprint making software that covers all package nuances or do packages like below- me, I design all 3D stuff by myself.

robertferanec , 02-17-2016, 10:43 AM

@EVW13 Thanks. I heard also some other people to say, that it is very useful and worth the money. But I have not tried it.

What do you use for 3D? The models look fantastic!

EVW13 , 02-17-2016, 11:21 AM

PLE is worth of trying as it greatly simplifies footprint creation according to IPC-7351 and in most of cases result doesn't require post-editing. Take a look also at this one- but keep in mind, this one is a different story and generally can't replace PLE(I tried both)- my opinion, the only real advantage of it is making schematic symbols from PDF.

For 3D modeling I use Solidworks- after all test-drives I realized that for me it's best software as my personal preference is nice and intuitive interface and thus, lack of “fighting with software” in the end of the day. Making 3D stuff in it is extremely easy and logical -also, I use it for color restoration for those models supplied by manufacturer: pretty often they have omitted colors, and it's reasonable to at least identify conductive elements and surfaces for better visual recognition and control- as the example you can see that USB footprint in this thread, as the attached footprint contains model with restored colors. And of course it helps a lot to make and check footprints- specially if you're not using EDA with nice mechanical snaps, good example is Allegro: imagine that you need footprint like below- making it in allegro “straight” way is just a waste of time, but with using MCAD it's really simple.



​ Here is other example of custom 3D model and custom footprint for very commonly used package- TDSON-8(also done in allegro)

robertferanec , 02-17-2016, 11:38 AM

@EVW13 Thank you very much. Very useful tips and links.

mairomaster , 02-18-2016, 03:52 AM

I have worked both with Altium IPC wizard and PCB Library Expert. I also have access to the official IPC-7351B standard. I also think that PLE is made very well and it is quite professional - I have checked its calculations and compared them to the IPC standard and it seem pretty accurate. I have achieved good results with Altium IPC wizard as well, but I agree that it is not quite as powerful and it does some magic behind the scenes which is not very clear to the user.

To achieved good results, the user need to have good understanding of the IPC standard with either of the tools. It is very important to enter all settings right (and there are many of them) in order to achieve a proper footprint. Also the user needs to have a detailed information from the manufacturer about the particular part in terms of sizes, tolerances, etc.

I was a bit surprised by the difference in the footprints of 0805 capacitors demonstrated by EVW13. I repeated the experiment using Altium 16 and PLE 2012. I used exactly the same input settings for both programs. Here is the result:



The dimensions of the pads and the courtyard are exactly the same, with one exception. Altium uses less space between the pads, which accounts for bigger variations of the capacitor's contacts inner spacing. I spent quite some time figuring out how exactly Altium does this calculation and realized it uses a formula slightly different than the IPC standard (but only for the pad spacing - everything else is the same). This approach seems to be the more reliable one, since in practice there is a slight chance that the capacitor contacts will be spaced closer than the IPC way of calculating it. However, that could lead to other problems as well, like having not enough solder mask between the pads which may lead to shorts in some cases.

If you are interested I can explain more about the different ways of calculating this particular dimension (and others maybe) but the mathematics is reasonably involved and somehow boring.

I am assuming EVW13 didn't use exactly the same input settings for the 2 footprints, hence the bigger difference.

EVW13 , 02-18-2016, 04:28 AM

In fact it's far not the first time I recognize such difference between FP and PLE- but I should advise you to test your settings in modern PLE version(2015.21): you will get exactly the same results as me. I use 2015.20 and generally it provides significantly different results compared to FP- and those result correlate with reality really nice, never ever I received issues report covering PCB assembly.

It's also worth to note that modern PLE calculates footprints according to IPC-7351C.

mairomaster , 02-18-2016, 05:16 AM

Yep, that could be the reason for the differences as well I have the feeling though, that Altium still uses IPC-7351B (maybe I read it on the Altium forum at some point as well). That would also explain the difference with the new PLE.

zeino , 02-18-2016, 04:43 PM

Wow this is more information than I could have imagined regarding IPC and footprint. Thank you very much for the info and sharing your experience. I like to ask you what would you suggest for my situation. In other words how should I proceed with my footprint libraries as a newbie. I like to follow a correct procedure. I will end up buying the Altium license for my startup in a year and will keep the license so I like to build the foundations correctly.

With the differences you mentioned between PLE and IPC Wizard and the fact that, I would like to build my footprints such that I can be sure I would not have manufacturing problems and be as close to IPC as possible. Without having enough IPC knowledge and not having the document what path for building my footprints do you suggest? At the time I downloaded PLE but seemed very detailed. Do you think following Altium IPC wizard despite its lagging behind the latest IPC would be a good idea? Just because it is the shortest path to IPC?or do you suggest I put effort learning PLE and IPC and use PLE?

The 3D modeling is amazing. Thanks for the tips and links. Seems I still have a long way to go.

May be after I read IPC, I can ask my doubts on calculations from you. Thanks again.

mairomaster , 02-18-2016, 05:25 PM

It is a difficult situation, especially for a beginner (I was in the same situation half an year ago). If you want to be serious with this (and I think everybody should be quite serious when creating a base library of parts) it is worth it to at least buy the IPC standard. It gives you a good understanding of how different sizes are calculated and other useful things. However, even if you have the information, it is quite inconvenient to do all the calculations manually when creating the components. You can make mistakes, either by miscalculating numbers or due to a lack of proper understanding of particular issues.

PLE is without doubt a great tool for creating a library, probably the best existing one. The full version which allows you to export components to Altium, etc., might be quite expensive though and I am not sure if the price would be justified for you. About the effort of learning it, it is worth it without a question. And it is not massively complicated anyway, if you already have some understanding of the standard. In many different topics in engineering it is a must to be as knowledgeable as possible, if you want to be a solid engineer.

As already discussed, the Altium IPC wizard is not a bad tool as well, in my opinion. Altium 16 also generates nice 3D models for you. However, due to it's shortcomings you have to be quite careful. A good understanding of the IPC standard and cross referencing reliable existing footprints definitely helps to double check if the footprints generated by Altium are alright.

Which tool you will select depends on your preference, your budget, how many footprints you will need to create, etc. Also keep in mind that for a lot of components the manufacturer specifies what footprint needs to be used and normally is good to go with that one, rather than going with the one suggested by IPC.

Even if you are an expert in IPC though, unfortunately it is not always the holy grail, and it is not perfect in all situations. I have been editing/checking some BGA footprints a few month ago and according to IPC they were supposed to have unreasonably big pads. The manufacturer was recommending pads that are quite a bit smaller, although it seemed to be quite an ordinary BGA package. We decided to go with the manufacturer's recommendation rather than IPC and now the board using those footprints works great. If we went with IPC recommended sizes it might have been working well again, but we would not have had enough space to run tracks between the pads for example.

EVW13 , 02-19-2016, 12:55 AM

zeino, at least you can try PLE light and see what values it puts in final footprint- and/or run trial to get full library during the trial time: it's enough to build entire EIA packages family at the very least. What about IPC-7351 standard, it's worth to mention that in case of purchasing PLE you'll get free copy of it- but I want to cover this in context of mairomaster's words about non-ideal results under some circumstances: me, I always develop 3D for footprint because 3D checks footprint and vice versa, and some time it's clear that for example manufacturer's footprint is wrong, or calculated one isn't good enough- meaning PLE, I had some non-ideal footprints with side concave package, footprint pads didn't cover physical pads properly.

What abour3D modeling itself- like it was said, there is no such software that covers all package nuances even for standard parts, so building stuff by your own is really great way as you gain control of the situation. Of course it's possible to search some free stuff on sites with 3D models, but my opinion it's not really good approach- there are a lot of authors which have their own very specific understanding of what is right and what is wrong, there are bunch of different methodologies and placing all such parts made different way makes you PCB look like mess. And I should say that control level is so high that you can even make parts which have bad or missing drawings in datasheet- here is example: BK-18650-PC4- incomplete drawings(for making 3D) and dummy original model(plain box).

ljo , 07-24-2016, 06:05 AM

How do you get the maxsize of the component for example for a smt capa? I learned from your course that you use this pdf (https://www.ibselectronics.com/pdf/p.../smt_notes.pdf) for the footprint. Do you use the F and G value in the table to define the top overlay line?

For my project I use CircuitMaker and I dont know if i have to trust the footprint done by someone else. It seems that anyway I have to draw at least silkscreens for the assembly drawings. And for some components for example they use courtyard layer. I didnt kwnow what it is. It is confused for me. Is this layer is mandatory for the assembly and also layout (placement)? can we just do as specified by Robert Feranec in his course(top overlay for placement)?

robertferanec , 07-25-2016, 06:54 PM

Yes, we use F and G, but when you are creating new components you may want to check if it fits there. Especially capacitors or beads may have different size occasionally.

Altium doesn't support courtyard directly, that is why I do no really use it and we only use the overlay layer instead. In Altium, I normally use 3D models to check if everything fits ok. In the previous company, where I used to work, they used Allegro and they always created courtyard.

ljo , 07-26-2016, 06:28 PM

Do you mean for checking if components fits i have to print the assembly and buying the components and puts all of them on the assembly drawing paper?
For the assembly it seems that the courtyard is not mandatory, am i right? When the courtyard is necessary, isnt it for placement only? And in your course you use top overlay as courtyard, right?

mairomaster , 07-27-2016, 01:44 AM

I will try to summarise:

The courtyard is mainly used to ensure proper physical spacing between the components. If you don't have enough space between them, you risk to have problems during the assembly process, due to imperfections of the pick and place machine and variance of components' actual size. For electrical spacing different rules are used (e.g. copper to copper, minimum solder mask sliver, etc).

Assembly houses don't normally need the courtyard information for the assembly process - the courtyard just helps you to create a design which could be assembled without problems.

I personally prefer using a separate layer for the courtyard as it gives me more flexibility and the ability to do whatever I want with the silk screen. I also use the courtyard layer for assembly drawings.

ljo , 07-27-2016, 08:51 AM

Thanks a lot for these precious information.

I was just a bit confuse because in the robert feranec 's courses he didnt mention courtyard. Now it is clear.

EVW13 , 07-28-2016, 09:13 AM

Hi guys,

Let me add few comments regarding mentioned subjects:

Yes, and this is significant fault of Altium- it does recognize courtyard as the entire footprint, means it allows overlap when rules covering gap between components are set to 0. You can compare it with Allegro, where “Placement Boundary” layer is courtyard layer- take a look at pic from attachment: if one try to overlap those boundaries that will give an error, however courtyard edge overlaps are allowed- which is correct and logical obviously. So Altium sucks here

Correct, it's not required for assembly completely, you only need it at design stage.

If you mean duplicating courtyard geometry also on silkscreen layer that generally is only possible when you use N and M pattern density according to IPC-7351, while in case of L you most probably will not be able to make such contour without violating “Silk-to-Copper distance”-like rules.

Meaning the exact requirement in courtyard definition: biggest benefit of it is possibility to achieve most dense placement while still remaining with IPC-7351, but it's obvious fact that far not all boards require that kind of placement. I'll tell you more, lot and lot of board are physically just oversized(artificially) to perform fast and easy component placement using grid- it's standard and mainstream approach, but it doesn't work in true high density designs. At the same time, placing components courtyard edge-to-edge in 90% of cases will lead you to high-end HDI designs area, but it's not main case: such placement isn't based on grid but on geometrical transformations thus being most complicated and time consuming method- however bringing the most high quality result by all means. If one doesn't have experience in such placement it's very easy to mess with your project in such way that will definitely turn into deep relayout/redesign

mairomaster , 07-28-2016, 09:47 AM

I meant I keep the two layers completely independent - each of them serves its own purpose. The courtyard is used for placement information/guidance as you explained and the silk screen is used purely for user information.

I agree that if only silk screen is used for courtyard purposes, you can't really have small L components, since you will not be able to meet the silk screen clearance (don't have time now to double check that).

With small resistors and capacitors I don't have silk screen at all. With some big component (ICs for example) the silk screen shows the body outline, while the courtyard is sort of an extended version of the body outline.

ljo , 07-30-2016, 08:20 AM

thanks for all these information.

1) But I dont understand what does it means "N, M or L pattern density according to IPC-7351"?

2) In which case am I? I am designing a simple board (soc ti am3358 + sd card + ddr3) just to make my first PCB and learn. The pitch of the soc is 0.8mm. I placed all the 0402 decoupling capacitors under the SOC.



3) I took a 0402 cap 10nF from the circuitmaker community. But I dont really understand, there are three versions of the footprint. I suppose a N, M and L version. And which one can i use to be able to place my capa correctly without overlapping each others?



4) And for all the footprints, there is something strange for the soldermask it seems that there is only one soldermask and not two. Is it correct?



5) Last question, how to be sure that these footprint are IPC-7351 compliant? I downloaded PLE free version. Can I compare metrics of the footprint with footprint generated by PLE? Or maybe is it better to regenerate the footprint with the component wizard? For info i use CircuitMaker so I think i cant generate footprint for it. Maybe im wrong?

EVW13 , 07-30-2016, 09:18 AM

Hi ljo, please review my comments below:

1) N-Nominal, M-Most, L-Least, all these are pattern density definitions covered by IPC-7351. You said you downloaded PLE- you can check them in tab “Terminal->Density level”.

2) According to you your pic I strongly believe than L density will serve the best. However those footprints don't look like IPC-7351 compliant: subject was covered few posts earlier.

3) Yes, all those 0402 footprints are kind of “Circuitmaker understanding of IPC-7351”- once again, you can run your own calculations via PLE and then compare and see differences (they do exist). What about overlapping- while you're still doing correct placement density level doesn't matter, courtyards shouldn't be overlapped(except edges) under any circumstances. Also, just to repeat myself: courtyard edge-to-edge placement is gridless in general and only can be achieved by geometrical transformations.

4) I don't understand, can you explain?

5) See p.1, just run your PLE and compare results.

P.S. If it's your first project I strongly recommend you to start from SMPS layout: there is no challenge in routing DDRx memories when you do understand design guidelines, however polygonal layout(Power and Ground + Switching nodes) is exactly kind of thing where 95% of PCB designer fail. Particularly it looks most weird in designs made with Allegro: all high-speed stuff is made really nice, and the rest including polygonal layout is just a crap. It will be also really good to learn how to do footprints for parts like on pics below(my own 3D models are attached), of course with overriding manufacturer's recommended land pattern.

ljo , 07-30-2016, 06:53 PM

[QUOTE=EVW13;n3411]Hi ljo, please review my comments below:

2) According to you your pic I strongly believe than L density will serve the best. However those footprints don't look like IPC-7351 compliant: subject was covered few posts earlier.

if i understand L version is for high density placement so i my case under the GBA. If i use L version I hope i will have no problem with the assembly . I will not assembled by hand i will send the board to a company specialized in assembly. do you think it will be ok?

4) I don't understand, can you explain?

I tried the component wizard in circuitmaker for a cap0402. you can see the result in the picture:


i see there is a difference in the solder mask layer compared to the capa in the community:



it is normal? what is the right way?

ljo , 07-30-2016, 07:23 PM

I have also question about capa0402 from the community. For the L and N version, the 3D model seems to be larger than the pad in the L version. Is it normal? See the picture below:
L version:

N version:

EVW13 , 07-31-2016, 07:43 AM

If you do nice courtyard and do placement without overlapping there will be no problem at all.

In terms of PLE output(copper/geometry) all they looks wrong, however upper one looks more realistic compared to lower. I've noticed that wizard from Altium/Circuitmaker tries to arrange pads mostly under package for L, which is strange. And meaning soldermask openings for 0402: 0.05mm is good start, less is better, more isn't acceptable- on your pic opening is greatly oversized.

If 3D models are really different that is serious mistake.

Tom Yunghans , 11-25-2020, 10:33 PM

I have also been quite confused about “courtyard” vs. “overlay” and their role in component placement. Most of the comments in this thread have been from 2016, before I started using Altium, so I’m not sure what may have changed. Altium has a component clearance DRC rule, which is used to flag errors if components are placed too close to each other. I do not have the IPC7351, but here are my conclusions after watching a couple of videos from Altium.

courtyard video: https://www.youtube.com/watch?v=Qhe8BgAFokc
courtyard summary: The courtyard outline is supposed to extend beyond the worst case boundary of the component, including any pads. How far beyond is a function of the footprint density level (maximum=0.5mm, median=0.25mm, minimum=0.1mm).

silkscreen overlay video: https://www.youtube.com/watch?v=ILX1ruslczc
silkscreen overlay summary: The overlay outline is supposed to follow the outline of the component body and be visible when the component is placed on the board. It should only follow the outline of the body of the part and not the pads. This is somewhat limiting for small discrete chips, as the overlay cannot overlap onto the pads. Footprints for small devices like 0402 or 0201 will not have any overlay outline at all.

Here is how I believe that Altium (AD20) determines if there is a violation of the “component clearance” requirement in the DRC rules:

1. If there is a 3D model for the component(s) it uses the edges of the 3D model.
2. If there is no 3D model, but there is a courtyard outline, it uses the courtyard outlines.
3. If there is no 3D model and no courtyard outlines, it estimates the size of the components, but it never appears to use the overlay outline.

It seems like many designers are making their silkscreen outlines surround the entire component instead of just the component body, and then using that silkscreen outline as the guideline for component placement instead of using the courtyard outline. Maybe this is more of a legacy approach? Is the courtyard a newer concept?