Connecting multiple power rails to a voltage rail
gyuunyuu1989 , 10-15-2023, 05:54 PM
I have so far not found any video that specifically deals with this topic.
FPGA's contain a whole lot of voltage rails, I/O buffer voltage supply per bank, core voltage, PLL analogue supply, maybe even voltage rail for MGBT transceivers. Then other components like DDR3 RAMs will require their own voltage rails as well which are clean.
I found that the FPGA board power planes are split into sections marked 3.3V, 1.8V, 3.3V_PLL, 3.3V_1O, 2.5V. There is another power plane that has a large 5V area that is output from some SMPS and another 5V area that is from the input voltage connector.
This raises several questions. How is it decided how to split the power plane? The voltage regulator can go only on top or bottom layers so it will need vias to connect to internal layers anyway. All the voltage regulators cannot be one one side of the board. if the FPGA needs so many voltage rails that are not shared by other components then it makes sense to actually generate them close to the FPGA itself.
We can connect the power rail on top layer too so why have an area on power plane dedicated to it?
When I ask how is it decided how to split the power plane, I mean to ask is, how to know where to make the splits and dedicate an area of copper to a voltage rail?
FPGA's contain a whole lot of voltage rails, I/O buffer voltage supply per bank, core voltage, PLL analogue supply, maybe even voltage rail for MGBT transceivers. Then other components like DDR3 RAMs will require their own voltage rails as well which are clean.
I found that the FPGA board power planes are split into sections marked 3.3V, 1.8V, 3.3V_PLL, 3.3V_1O, 2.5V. There is another power plane that has a large 5V area that is output from some SMPS and another 5V area that is from the input voltage connector.
This raises several questions. How is it decided how to split the power plane? The voltage regulator can go only on top or bottom layers so it will need vias to connect to internal layers anyway. All the voltage regulators cannot be one one side of the board. if the FPGA needs so many voltage rails that are not shared by other components then it makes sense to actually generate them close to the FPGA itself.
We can connect the power rail on top layer too so why have an area on power plane dedicated to it?
When I ask how is it decided how to split the power plane, I mean to ask is, how to know where to make the splits and dedicate an area of copper to a voltage rail?
gyuunyuu1989 , 10-24-2023, 06:27 PM
Here is screenshot of the L7 [PWR] of the Robert's course's iMX6 Rex V1I1.
I can see that the different sections are connected to nets like +SATA_VP, +1V2_VDD_ARM_CAP, +2V5_VDD_HIGH_VPH, +VDDUSB, +PCIE_VPH, +PCIE_VPTX among others. Is there a way to know from the PCB view itself, what is the voltage source and what components does this feed? In other words, just from the PCB view, identify the source of the voltage and the components that it feeds.
This PCB is very extremely totally complex that I am having trouble looking at what is there on it. There are so many layers that everything looks jumbled up. If I hide the layers, everything of that layers disappears. When I do make them visible, the thing looks confusing. I did not know that complex boards can be so difficult to manoeuvre in the PCB view.
The schematic does not show what vias and nets and pours are used to connect stuff. Therefore, it is not possible to get this information from the schematic.
From schematic it is not possible to make a flow chart like this:
U32 (VRM) [X,Y= ###] -> Net (3v3) -> TH Via (3v3) [X,Y=###] -> Polygon (3v3) -> Blind/Burried Via [X,Y=###] -> Net (3v3) -> U1 (pin A16) [X,Y=###]
I can see that the different sections are connected to nets like +SATA_VP, +1V2_VDD_ARM_CAP, +2V5_VDD_HIGH_VPH, +VDDUSB, +PCIE_VPH, +PCIE_VPTX among others. Is there a way to know from the PCB view itself, what is the voltage source and what components does this feed? In other words, just from the PCB view, identify the source of the voltage and the components that it feeds.
This PCB is very extremely totally complex that I am having trouble looking at what is there on it. There are so many layers that everything looks jumbled up. If I hide the layers, everything of that layers disappears. When I do make them visible, the thing looks confusing. I did not know that complex boards can be so difficult to manoeuvre in the PCB view.
The schematic does not show what vias and nets and pours are used to connect stuff. Therefore, it is not possible to get this information from the schematic.
From schematic it is not possible to make a flow chart like this:
U32 (VRM) [X,Y= ###] -> Net (3v3) -> TH Via (3v3) [X,Y=###] -> Polygon (3v3) -> Blind/Burried Via [X,Y=###] -> Net (3v3) -> U1 (pin A16) [X,Y=###]
qdrives , 10-25-2023, 02:42 PM
Have you ever done Ctrl-click on pads, tracks, via's, etc?
That will highlight the selected net.
That will highlight the selected net.
gyuunyuu1989 , 10-25-2023, 05:14 PM
You are correct, but there is a problem.
This is the first time in my life that I am seeing a board with 12 layers. There are so many signal layers. There are so many power layers. The whole PCB view looks cluttered. I do not even understand how a human being can design something with so many layers since its so hard to keep making layers visible and invisible from "View configuration" to see where something is going as it travels from one layer to another. Things travel from one layer to another, and another and another. Via and track and via and plane and via and track. When all layers are on, they are on top of each other and it becomes impossible to see what is going where.
Basically, I am not sure how to really do what you are saying with this type of complex board with so many signal and power layers, one on top of another.
This is the first time in my life that I am seeing a board with 12 layers. There are so many signal layers. There are so many power layers. The whole PCB view looks cluttered. I do not even understand how a human being can design something with so many layers since its so hard to keep making layers visible and invisible from "View configuration" to see where something is going as it travels from one layer to another. Things travel from one layer to another, and another and another. Via and track and via and plane and via and track. When all layers are on, they are on top of each other and it becomes impossible to see what is going where.
Basically, I am not sure how to really do what you are saying with this type of complex board with so many signal and power layers, one on top of another.
qdrives , 10-26-2023, 02:28 PM
First hide all Gnd layers. Also hide all none essential layers (3D, solder mask, paste mask, drill, etc.)
Then set transparency for all objects to about 50%, especially polygons (70%).
Play with the dim and mask levels too when navigating.
Then set transparency for all objects to about 50%, especially polygons (70%).
Play with the dim and mask levels too when navigating.
gyuunyuu1989 , 10-27-2023, 04:22 AM
I did not know that we get could change the transparency of objects. Where is the setting for that?
So do I understand correct that Altium can't give a flowchart for how something is routed in the PCB view?
So do I understand correct that Altium can't give a flowchart for how something is routed in the PCB view?
gyuunyuu1989 , 10-27-2023, 01:50 PM
OK, so from what you wrote:
First hide all Gnd layers. Also hide all none essential layers (3D, solder mask, paste mask, drill, etc.)
I understand how to do this, from the View configuration, I just use the eye symbol to switch off some layers.
Then set transparency for all objects to about 50%, especially polygons (70%).
How is this done?
Play with the dim and mask levels too when navigating.
Could you kindly elaborate? When we use PCB filter, things become dim or masked. When we use single layer mode, things become dim and masked.
Thanks.
First hide all Gnd layers. Also hide all none essential layers (3D, solder mask, paste mask, drill, etc.)
I understand how to do this, from the View configuration, I just use the eye symbol to switch off some layers.
Then set transparency for all objects to about 50%, especially polygons (70%).
How is this done?
Play with the dim and mask levels too when navigating.
Could you kindly elaborate? When we use PCB filter, things become dim or masked. When we use single layer mode, things become dim and masked.
Thanks.
qdrives , 10-27-2023, 03:51 PM
In the View configuration panel, select the tab View Options.
There is the transparency of the objects. I would also suggest the Advanced view and set the transparency of layers, mainly the overlay layers.
Below you also see the "Mask and Dim Settings".
As for your "flow" -- that is why I mentioned Ctrl-(shift)-click.
There is the transparency of the objects. I would also suggest the Advanced view and set the transparency of layers, mainly the overlay layers.
Below you also see the "Mask and Dim Settings".
As for your "flow" -- that is why I mentioned Ctrl-(shift)-click.
gyuunyuu1989 , 10-27-2023, 04:17 PM
The "View Configuration" panel has been mentioned in many many videos that I have seen. But not a single video ever discussed the "View Options" or the "System Colors" and this just made me ignore these two as being no important. Come to think of it, only the "View Configuration" panel actually has tabs. I have not found tabs on any other panel yet.
But today, thanks you to you, I understand how important these two are.
But today, thanks you to you, I understand how important these two are.
qdrives , 10-28-2023, 09:32 AM
At least the "Properties" panel also has tabs. And the properties panel depends on which properties too.
gyuunyuu1989 , 10-28-2023, 04:16 PM
Yes, I discovered that depending on what we select, a tab might appear in the properties panel as well.
katepalmes , 11-13-2023, 07:13 AM
Develop the backend infrastructure to support location data storage https://mlsdev.com/blog/how-to-creat...tion-based-app, processing, and any server-side functionalities. Ensure that your backend system is secure, scalable, and capable of handling the demands of your location-based app. Testing: Rigorously test your app, especially its location-based features. Test in various real-world scenarios to ensure accuracy and reliability. Pay attention to battery usage, as continuous location tracking can impact device battery life.
qdrives , 11-15-2023, 03:10 PM
@katepalmes It is up to you to determine if 'this' works for you. It is merely how you view the board.
gyuunyuu1989 , 11-15-2023, 06:51 PM
The question was supposed to be "Connecting multiple power rails to a voltage planes"
Use our interactive Discord forum to reply or ask new questions.