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noisepic , 07-25-2017, 10:42 PM

Hello,

​When design DDR3 I intend to add test pad/ via to see eye diagram of DDR3 signal, but I know that add via mean introduce some mismatch and make SI worse. Lacking of via I will don't know what happen in DDRx signals. The consideration should be choose size of pad/via to minimize the affect? Is there any good solution?

mairomaster , 07-26-2017, 01:44 AM

The first option is to use the standard signal vias, which you need for routing the signals. For signals running on the top layer you can easily add test points on top of the tracks, so you don't have big stubs. I've used those two methods.

If you really need to have test vias on the rest of the signals (let's say you use micro vias and don't have access to them for that reason) maybe you can use as small vias as possible. It will help if you create large opening for the vias (antipads) on the different plane layers - that reduces the impedance of the via.

Before the whole thing, make sure you have an appropriate high-speed oscilloscope to do the measurements.

noisepic , 07-26-2017, 01:50 AM

How big size your test via on the track?
My DDRx trace width 4mil and also need Active probe to minimize the parasitic element. I'm afraid microvia affect to eye diagram.

mairomaster , 07-26-2017, 05:42 AM

I haven't used test vias. I used 1mm test points placed directly over the tracks.

I didn't get the part about the micro via?