FEDEVEL
Platform forum

kullboys , 10-03-2018, 01:24 AM

Hello,

When I read something about DDR3 design recently, I had two questions about DDR3 termination.

First, as far as I've learned, DDR3 termination is used for better signal integrity, especially in DDR3 fly-by architecture. Can I understand it in this way? If I use a T-blanced topology for multiple DDR3 chips (like IMX6 Rex), or if I just use one DDR3 chip, I don't need termination resistors, and VTT (termination power) can also be removed. Is that right?

My second question is: if termination is used, how do I deal with the trace between DDR3 pins and termination resistors when I do the length matching? Shall I also include it in length matching, or can I just ignore it? Since I feel the trace between DDR3 pins and termination resistors will have no impact on the time during which signals travel from CPU to DDR3 chip.

Thanks.

Paul van Avesaath , 10-03-2018, 07:32 AM

1) it is my understanding that termination should always be applied in DDR3 FLyby. But never did a T-branch on ddr3.
I checked a DDR2 T-branch design and there i had no termination on the ADDR/CMD/Control lines.

2) just keep the traces as short as possible, dont bother with length matching the traces from end point to terminations.(did DDR3 and DDR4 fly by this way, simulation shows no issues)

just route your DDR3 with length matching.. lastly add the termination resistor and route those as short as possible,

mind you my designs mostly interact with FGPA's don know the exact spec of micro processors, maybe it is different there..

robertferanec , 10-08-2018, 02:01 AM

I just would like to add to @Paul van Avesaath's answer.

Very simply to say:

​The structure of balanced T-Branch routing is a kind of helping with eliminating reflections in the tracks, so you may not need termination. However, with no termination you can not go to very high frequencies and the tracks should be short.

The Fly-by requires termination, otherwise you would get reflection from the end of the long tracks which are usually far away from CPU pads. Once you put there the right termination, reflection is minimized and you can run the bus on higher frequencies than T-Branch.

Tammaro , 11-12-2018, 01:20 PM

What's the 'right termination,' Robert? I'm a bit confused.

robertferanec , 11-13-2018, 02:38 AM

@Tammaro, the right termination depends for example on track impedance and pin impedance connected to this track. The right termination is usually simulated, calculated or recommended in design guides or reference schematics.

michaelchang , 11-14-2017, 10:33 PM

Hello,

When I read something about DDR3 design recently, I had two questions about DDR3 termination.

First, as far as I've learned, DDR3 termination is used for better signal integrity, especially in DDR3 fly-by architecture. Can I understand it in this way? If I use a T-blanced topology for multiple DDR3 chips (like IMX6 Rex), or if I just use one DDR3 chip, I don't need termination resistors, and VTT (termination power) can also be removed. Is that right?

My second question is: if termination is used, how do I deal with the trace between DDR3 pins and termination resistors when I do the length matching? Shall I also include it in length matching, or can I just ignore it? Since I feel the trace between DDR3 pins and termination resistors will have no impact on the time during which signals travel from CPU to DDR3 chip.

Thank you!

robertferanec , 11-15-2017, 08:20 AM

1) Yes. You can compare schematics of iMX6 Rex module (T branch) with OpenRex (fly-by):
- iMX6 Rex module schematic: http://www.imx6rex.com/wp-content/up...-Schematic.pdf
- OpenRex schematic: http://www.imx6rex.com/wp-content/up...Production.pdf

The important point is, that when you are using termination resistors you will get better quality signal => you need to used termination resistors on memory interfaces running on higher frequencies (e.g. I think probably the highest frequency for T branch DDR3 what I used was 533MHz). Advantage of T-branch is, that you can save some space. Also, before you decide to use T-branch, you may want to be sure that the chip manufacturer mentioned T-branch support in their design guide (or you may want to ask them).

2) Keep the distance from last memory chip to termination resistor short. This distance is not included in length matching. Your length matching is based on: CPU to each individual memory chip. The termination is last segment in the net (have a look at OpenRex layout, that can help).

If you are not sure about memory layout, it is always very useful to check JEDEC reference designs (you need to register, but you can download memory module schematics and layouts for free): https://www.fedevel.com/welldoneblog...yout-examples/

michaelchang , 11-15-2017, 02:56 PM

Thanks Robert for your advice, it's very helpful.

Mihai , 05-10-2019, 01:46 AM

Hi,

@robertferanec when placing the termination resistors at the far-end, after DDR3, should be also length matched with respect with the other termination resistor traces on this sector? I am aware that between the controller and DDR3 all the control signals should be length matched.

Thanks,
Mihai

Paul van Avesaath , 05-10-2019, 03:26 AM

no it is not a criteria for the termination.. that said I would not reccommend a very large difference.. try and keep them similar and you good to go... maybe some one else thinks diffferently but i have done a lot of ddr3 designs doing it like that and never had a problem with them w.r.t. termination resistors..

For the CLK pairs I would reccomend that they should be as close to the pins as possible and matched...

Mihai , 05-13-2019, 12:10 AM

Hi @Paul van Avesaath

Thanks for your info. I will try to keep them pretty equal.

cheers,
Mihai