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Danie , 12-10-2025, 04:22 AM

Design info: I need to design two PCBs. My main PCB contains the MCU and all its I2C connections, and I need to design a second small PCB which will have a ToF sensor that will need to communicate to the MCU on the main PCB via I2C. The second PCB is going to be connected roughly 8cm away from the main PCB. I2C communication will be at 400kHz, and I will connect power and gnd from the main board to the second board via the connector.

What are the key PCB design rules I'm going to need to consider for both boards? I've never designed two boards and had them connect with each other before and my research has left me confused... Since I'm designing the second PCB later which means the second board WON'T be connected to the main PCB for a while, how will this affect the pullup resistor value required and the I2C line depending on if it's plugged in or not?
My interpretation is that I'll be creating a stub on the I2C line at that connector point when it's not plugged in, but I'm not sure how to address this either...

QDrives , 12-12-2025, 08:43 PM

The most important thing to consider is ESD protection.
If you want, you can add a buffer for the external connection:
https://www.digikey.nl/en/products/filter/interface/signal-buffers-repeaters-splitters/756?s=N4IgjCBcoCwAwFYqgMZQGYEMA2BnApgDQgD2UA2iAOwCctAzAGwjH0KM1gAcLIXcAJjj9etLgjhxe-IVwjEqCATCEgAusQAOAFyggAytoBOASwB2AcxABfW0A

tomas.kaplan , 12-19-2025, 09:24 AM

Hey, i would consider the rise time / fall time of your SCL/SDA edges. If you are using 400kHz clock, there is 300ns maximum rise time requirement. You can measure it via oscilloscope. From my experience, falling edges are not the problem usually, the rising edges are. Rise time increases with capacitive loading of your bus. The more devices on the bus and the longer the bus is, the more capacity loading there is. You can counter this problem by decreasing value of your pullup resistors. To allow more current to "charge" the capacity. With the cost of current consumption. I have recently designed I2C bus across 2 pcbs connected together by cable, almost 40cm long with 8 I2C devices. Luckily it was running on 100kHz so the risie time limit was little bit easier to meet.