FEDEVEL
Platform forum

Emadul Hasan , 08-18-2025, 12:21 PM

hello everyone,
Good day!

I am working on a project RK3399 Based SBC. Currently I'm freeze at making fanout of DDR byte lane 0. But with my current SoC pin layout i cannot figure it out. How can i do that.

Can i lay out this way?
DQ--Top layer
DQS-- Inner layer
DM-- Inner Layer
Later i will match their delay.

or i have to keep them in same layer?

@Phil
@Robert Feranec
Currently i am enrolled in Advanced digital hardware design course.