DDR3 timing
Blackmagic , 05-31-2018, 11:09 AM
I’ve been learning a lot from your board files, your open source community is great. I had a question. When I simulate the ddr3 address lines in hyperlynx the address signals seem to lag behind the clk by about 100ps. I was under the impression with a tree topology as implemented on this irmx6 Rex that this would be a problem. Is this handled with some sort of write leveling or skew control on the software side?
robertferanec , 05-31-2018, 09:20 PM
Can you attach some screenshots? I think, ADDR is sampled on rising clk edge and it is changing around falling clk edge. ADDR signals should be little behind CLK as clock. But it may depend on settings.
Blackmagic , 06-01-2018, 09:37 AM
Here is a picture of the CLK vs ADD. Here the clock cycle is set at 1.875ns to simulate the max frequency the IMX6 can support for DDR3 writes roughly 533MHZ. The eye diagram for the positive line of the differential clock signal is shown just because it has the same reference as the ADD signal A10, it crosses this point at the same time the diff signal crosses 0. Now CLK is orange and A10 is light blue. As I was saying the CLK is ahead. Yes ADD is sample on the rising edge. What do you mean by "ADDR signals should be little behind CLK as clock."? Thanks
robertferanec , 06-01-2018, 07:30 PM
This simulation are not probably real waveforms - as you can see in the simulation CLK and ADDR are exactly same frequency. I believe, in reality ADDR will be hold for 1T or 2T depends on settings. How do you simulate the memory - did you use memory wizard?
Blackmagic , 06-04-2018, 12:58 PM
Well yeah CLK and ADDR would be the same frequency at 1T and 1 to 2 at 2T. I thought it would make sense to design towards 1T so the setting is available. I'm using Hyperlynx's standard simulator from the Run interactive simulator option. I discussed this with a Hyperlynx support engineer, he said the results would be relevant while the Wizard would be more convenient. I do not have the wizard otherwise I'd use it.
robertferanec , 06-11-2018, 11:21 AM
I believe, 1T should look more like this ( https://www.treepcb.com/pcb-ddr-desi...tching-timing/ ):
Or like this ( http://chipdesignmag.com/display.php?articleId=3481 ):
Or like this ( http://chipdesignmag.com/display.php?articleId=3481 ):
Blackmagic , 06-11-2018, 04:48 PM
Thanks these resources are helpful. I had a question though. In the tree resource. There seems to be some inaccuracies. They suggest making the address line longer than the clk which goes against every reference I have read. Then they mention that when they did this the address signal became 200ps slower than the clk(delay is directly proportional to length so that can't be) but the picture they show seems to have the clk delayed relative to its earlier position. I believe that what they actually show in the image is the address line getting shorter or the clk line getting longer. Also I resimulated the IMX6Q rex with a proper 1 T timing and obtained results that made sense. Thank you very much for your help.
robertferanec , 06-13-2018, 01:34 AM
They suggest making the address line longer than the clk
the picture they show seems to have the clk delayed relative to its earlier position
Blackmagic , 06-18-2018, 10:00 AM
I uploaded the segment I made reference to. Here my confusion is that the article seems to be saying that the second plot relative to the first plot has an adjusted address length longer than the original address line length.The address signal in the second plot is identical to the one from the first one though and the clock in the second plot has delay now relative to the clock in the first picture. They say they are slowing the address line relative to the clk but it looks to be the opposite. Am I misinterpreting this? I had another question I wanted to ask you as well . The JEDEC specification for DDR3 gives the table of setup and hold times for correlating slew rates. If your design has slew rates that are faster than the specifications are there any suggested ways to fix this?Thanks for your help Robert I really appreciate it.
robertferanec , 06-20-2018, 03:21 AM
In the first picture, the address will arrive a little bit sooner, as it is shorter ... and then clock will arrive.
In the second picture, they made address a little bit longer, so they slowing it down. In this case, clock will arrive first and then a little bit later address signal
I am not sure about slew rates, but you may be able to play with termination, that can help you to influence some parameters of the signals.
In the second picture, they made address a little bit longer, so they slowing it down. In this case, clock will arrive first and then a little bit later address signal
I am not sure about slew rates, but you may be able to play with termination, that can help you to influence some parameters of the signals.
Blackmagic , 06-20-2018, 12:38 PM
Yeah increasing the driving termination resistance brought the slew rates within the JEDEC specification. I had a question I don't think I have asked yet, maybe I have. The setup and hold times can be programmed in software right? What I mean is if I have the data strobe line and the data line laid out at the same length and with no adjustments the signals are arriving at the ddr chip at the same time, then a delay can be added to the data line so that it can observe its specified setup time relative to the data line?
robertferanec , 06-20-2018, 11:40 PM
I believe, the most common delay which is used for example in DDR3 memories is applied to the DQS. Data are then strobed by DQS. By applying the delay you are moving the DQS relatively to CLK.
This is called Read and write leveling. You can google for some info, e.g. here:
- https://daffy1108.wordpress.com/2010...read-leveling/
It is similarly possible to delay each DQ bit within a lane with respect to its strobe in order to perfectly center the strobe around the DQ signal. This feature is available more commonly in DDR4 controllers and in some of the higher-end DDR3 controllers. It is known by many names, including “per-bit leveling,†“DQ calibration,†or “DQ-DQS deskew†(say that 10 times fast!).
Source: https://blogs.mentor.com/hyperblog/b...ter-dq-timing/
This is called Read and write leveling. You can google for some info, e.g. here:
- https://daffy1108.wordpress.com/2010...read-leveling/
It is similarly possible to delay each DQ bit within a lane with respect to its strobe in order to perfectly center the strobe around the DQ signal. This feature is available more commonly in DDR4 controllers and in some of the higher-end DDR3 controllers. It is known by many names, including “per-bit leveling,†“DQ calibration,†or “DQ-DQS deskew†(say that 10 times fast!).
Source: https://blogs.mentor.com/hyperblog/b...ter-dq-timing/
Blackmagic , 06-27-2018, 03:41 PM
This might be a silly question. The Clk enable signal is part of the control group. Does this mean it should be length matched like the rest of the ctrl group? My thought was this would just be an assert high or low signal similar to nRST.
robertferanec , 06-29-2018, 06:46 AM
CKE is used when switching between ranks (you are using more ranks if you have more memory chips connected to the same data signals e.g. you have two memory chips connected to D0) and also to control some memory modes. So, if you are using ranks, you definitely need to control CKE. If you a re using single rank memory, I am not sure if you could simply keep CKE active all the time and if yes, what would be the impact to power consumption. If you are using CKE, it needs to be in relationship with CLK, so it is important how it is routed and length matched.
This is from https://www.altera.co.jp/ja_JP/pdfs/..._dual_ddr2.pdf
"The control group signals (chip Select CS#, clock enable CKE, and ODT) are only ever single rank. A dual-rank capable DDR3 DIMM slot has two copies of each signal, and a dual-DIMM slot interface has four copies of each signal. The signal quality of these signals is identical to a single rank case. The control group of signals, are always 1T regardless of whether you implement a full-rate or half-rate design. As the signals are also SDR, the control group signals operate at a maximum frequency of 0.5 × the data rate. For example, in a 400 MHz design, the maximum control group frequency is 200 MHz"
This is from https://www.altera.co.jp/ja_JP/pdfs/..._dual_ddr2.pdf
"The control group signals (chip Select CS#, clock enable CKE, and ODT) are only ever single rank. A dual-rank capable DDR3 DIMM slot has two copies of each signal, and a dual-DIMM slot interface has four copies of each signal. The signal quality of these signals is identical to a single rank case. The control group of signals, are always 1T regardless of whether you implement a full-rate or half-rate design. As the signals are also SDR, the control group signals operate at a maximum frequency of 0.5 × the data rate. For example, in a 400 MHz design, the maximum control group frequency is 200 MHz"
Blackmagic , 07-02-2018, 05:20 PM
Ha so I have yet another question Mr. Robert. I am working on the HDMI outputs and looking at a reference design from NXP, they are using a level shift ic from 3.3 to 5 v. I ran the NXP HDMI voltage data sheet SPECS against the HDMI 1.4 spec. and it appears that by using the proper 3.3v pull-up resistors on a few of the lines and then providing 5v power to the hdmi output connector it should be possible to meet the spec. Looking at the IMXREX hdmi design it seem that this was done and a level shift ic was not used. What is the purpose of the level shift in the NXP reference design(development board). I can see that it provides ESD protection but it would seem to shift some of the voltages out of spec. Is it possible reference the signals to 5v or 3.3 v?
robertferanec , 07-03-2018, 03:20 AM
Can you attach the NXP reference schematic (or screenshot of the schematic)?
Blackmagic , 07-05-2018, 01:03 PM
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robertferanec , 07-07-2018, 02:29 AM
This only shifts the DDC, for HDMI signals it is just ESD protection.
Blackmagic , 07-16-2018, 04:52 PM
In the imx6 hardware guideline it mention that differential pairs should be matched for some signal lines. I was wonder do they mean that the group of differential pairs should be matched to each other and each negative and positive signal in a signal pair should be matched or that just the negative and positive signal for a single pair should be matched. Here is the part of the guideline that I am referring to.
Blackmagic , 07-16-2018, 04:54 PM
In the guideline pic I posted above I was reffering to the length matching line: "Each differential pair should be length matched to =/- 5mils."
robertferanec , 07-18-2018, 08:55 AM
Often you will find recommendation to length match differential signals within pair (between negative and positive track) within 5 mils (so maximum difference between length of plus and minus track in same differential pair should not be more than 5 mils - and for very high speed signals this needs to be done on every layer).
We also make the length of differential pairs of an interface similar - so for example the whole group of differential pairs of LVDS would have similar length e.g. within 10 mils. It is not always required, but you do not know how cables will be done (some wires in cable may be longer, some shorter), so it may be safer to make them similar length.
I hope that helps you to answer your question.
We also make the length of differential pairs of an interface similar - so for example the whole group of differential pairs of LVDS would have similar length e.g. within 10 mils. It is not always required, but you do not know how cables will be done (some wires in cable may be longer, some shorter), so it may be safer to make them similar length.
I hope that helps you to answer your question.
Blackmagic , 07-18-2018, 11:56 AM
Yeah i think it does help me with my question, thanks. I was basically trying to resolve whether the manual was referring to your first point or your second. Either way I'll follow both rules.
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