FEDEVEL
Platform forum

Enginstud , 07-04-2023, 11:11 AM

Hi,
In SOCs IC, we have different voltages and the IC has several pins to sink the current for each voltage rails. But when we only have 1 small bypass cap (47nf in our case) for severals pins, should we place the cap in the center of the pin region, or favorising 1 pad by placing the cap next to it ? I am only asking for that very high frequency bypass cap of course.
See the pictures for an example with 1x47nf cap for 4 pads.

Thank you very much.

qdrives , 07-04-2023, 01:39 PM

Let me start with this article:


As for the high frequency - I would treat all these pin the same with a high capacitance small size cap.
Further away you can place a bigger high cap.
So a total of 5 caps.

Enginstud , 07-05-2023, 08:58 AM

Interesting, but for now, I'll still continue on with the schematic I have (using XIlinx recommended caps....) since it's my first advanced board, I'll follow the recommendations that have proven to work with that board.
That being said, I still don't know how to place the low value bypass cap in my case....

robertferanec , 07-11-2023, 04:23 PM

If you are not sure, have a look how they placed them on the reference board. Usually you place the lowest value capacitor closest to the pins (it can be middle) and then capacitors with bigger and bigger values can be placed further and further.

as @qdrives pointed out, that circuit may be a legacy ... it could be interesting to simulate it and you may find out, that the 47nf capacitor is doing not much (higher frequencies from the chip may not be able travel from the silicon to that capacitor due inductance in bond wires and VIAs)

qdrives , 07-12-2023, 01:42 PM

@robertferanec I was considering to state as well to put the lower cap (higher frequency) in the middle, but that would give it higher inductance to all pins and not lower for one. Just an idea.