FEDEVEL
Platform forum

Enginstud , 07-20-2023, 02:23 PM

Hi everyone,

I am considering bit swapping in my design, and I have seen in this video of Robert: https://www.youtube.com/watch?v=aySAg50S1E8 @17:40
That for write leveling purpose, we need to keep the lowest bit of our DRAM byte lane connected to the lowest bit position of the controller's byte, the remaining bits of the byte can be swapped freely.

For those who have experience with DDR memories, can you tell me if you are always considering this ? Are you always using Write leveling ?
For example, I have seen many design where it doesn't seem to be considered. I assume it is because Write leveling is not used ? Or that "Prime bit" doesn't matter anymore ?

Thank you very much everyone.

robertferanec , 07-23-2023, 05:18 PM

I am not sure about the prime bit, but we always do write leveling. Some designs may work without it, but they may not work the most optimal way (means when something changes e.g. temperature, the memory may start failing)

phils-lab , 07-24-2023, 01:16 AM

Speaking for AMD/Xilinx Zynq-based design, such as for the 'advanced digital hardware design' course, the bits in the Zynq DDR controller are ORd, so the prime bit doesn't matter as such. See the Zynq TRM page 361/362 for more info (https://sceweb.sce.uhcl.edu/xiaokun/...7000-TRM.pdf):

"Write leveling is performed independently for each byte lane. The calibration logic OR's the DQ bits in a byte to determine the transition because different memory vendors use different bits in a byte as feedback."

There is also an answer record on the AMD/Xilinx forums with this response (https://support.xilinx.com/s/questio...nguage=en_US):
"A JEDEC-compliant DDR3 memory controller has no such bit-swap sensitivity with write leveling, or with any other transaction or function.

Long technical explanation of DDR3 design and Jedec standard as it relates to this question:
The JEDEC DDR3 standard does not specify which DQ (in a byte lane) is to be the 'prime DQ'. By requiring all non-prime DQs to be '0', the JEDEC standard ensures detection of the 'prime DQ' by the controller.
DRAM device manufacturers are not obligated to establish or maintain a consistent and unchanging 'prime DQ' bit selection, or to match Micron's current design selection.
DIMM/SO-DIMM manufacturers are allowed to (and will) swap DQ signals within byte lanes, rendering DRAM manufacturer's prime DQ identification moot. Even worse, two-rank modules may have un-matched DQ swapping for each of the two ranks. [note: from JEDEC 21C -- DQ-to-I/O wiring is shown as recommended but may be changed.]
In order to maintain compatibility with various DRAMs and modules, memory controllers are obligated to detect any DQ bit which might be 'prime'.
This is rather an important issue.
The point of an industry standard (JEDEC JESD79-3E, for example) is to allow and ensure industry compatibility. The JEDEC DDR3 standards (devices, modules) do not specify a 'prime DQ'. JEDEC considers a specification of the 'prime DQ' unnecessary for industry compatibility."​

In any case, check out your memory controller datasheet, and memory part datasheet to be sure.