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Question on DDR crosstalk - Advanced PCB Layout Lesson 3
Tom Yunghans , 04-19-2020, 04:04 PM
Hi Robert,
I am working on lesson 3 of your Advanced PCB Layout Course. There is a lot of good material there, I especially appreciated the video showing the PCB manufacturing house building up a stack of cores and prepreg material.
I had a question about crosstalk on the DDR interface. I have attached the guidance you provided in the video for spacing to prevent crosstalk on the DDR interface. I looked at your original design for the processor module which you provided in lesson 1, and the distance to the closest reference plane for layers 3 and 10 is a little less than 0.1mm (0.092mm). The table you presented (attached below) implies that you need to provide spacings between signals on the order of 0.3mm for the Address/Command lines, and 0.4mm for the Data lines when the reference plane is 0.1mm away. I noticed that you were only able to accomplish spacings between 0.15mm and 0.2mm on those interfaces in your design. However, that is not really the question I have.
I am questioning whether the separation really needs to be enforced between signals within the same interface. For example, if two data lines in one of the eight data groups are routed right next to each other with minimal spacing, I think we can agree that there will be a significant amount of crosstalk between the two. However, since both of those data lines are changing at the same time, and clocked by the same clock, can it be argued that even if there is crosstalk, it wouldn't matter?
Your thoughts?
Thank you,
Tom Yunghans
I am working on lesson 3 of your Advanced PCB Layout Course. There is a lot of good material there, I especially appreciated the video showing the PCB manufacturing house building up a stack of cores and prepreg material.
I had a question about crosstalk on the DDR interface. I have attached the guidance you provided in the video for spacing to prevent crosstalk on the DDR interface. I looked at your original design for the processor module which you provided in lesson 1, and the distance to the closest reference plane for layers 3 and 10 is a little less than 0.1mm (0.092mm). The table you presented (attached below) implies that you need to provide spacings between signals on the order of 0.3mm for the Address/Command lines, and 0.4mm for the Data lines when the reference plane is 0.1mm away. I noticed that you were only able to accomplish spacings between 0.15mm and 0.2mm on those interfaces in your design. However, that is not really the question I have.
I am questioning whether the separation really needs to be enforced between signals within the same interface. For example, if two data lines in one of the eight data groups are routed right next to each other with minimal spacing, I think we can agree that there will be a significant amount of crosstalk between the two. However, since both of those data lines are changing at the same time, and clocked by the same clock, can it be argued that even if there is crosstalk, it wouldn't matter?
Your thoughts?
Thank you,
Tom Yunghans
robertferanec , 04-20-2020, 06:42 AM
For example, if two data lines in one of the eight data groups are routed right next to each other with minimal spacing, I think we can agree that there will be a significant amount of crosstalk between the two. However, since both of those data lines are changing at the same time, and clocked by the same clock, can it be argued that even if there is crosstalk, it wouldn't matter?
(and yes, you are thinking right - it would matter but the rules can be more relaxed)Use our interactive Discord forum to reply or ask new questions.