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Decoupling capacitor
Hung , 05-27-2020, 11:06 AM
Hi all!
I have a questions. Normally, i palace 1 capacitor /1pin power. Example DDR3 Mem, how many capacitor per 1 RAM ?
I have a questions. Normally, i palace 1 capacitor /1pin power. Example DDR3 Mem, how many capacitor per 1 RAM ?
mnpebm , 05-28-2020, 07:47 AM
Not a simple answer (to me at least). Check the data-sheet for the RAM chip.
In general, yes, if possible, one capacitor per power pin keeping as close as possible to minimize inductance.
This link has good information regarding values and placement.
https://www.maximintegrated.com/en/d.../5/5100.html#7
Good information here. Perhaps more than what you are looking for:
In general, yes, if possible, one capacitor per power pin keeping as close as possible to minimize inductance.
This link has good information regarding values and placement.
https://www.maximintegrated.com/en/d.../5/5100.html#7
Good information here. Perhaps more than what you are looking for:
robertferanec , 05-29-2020, 03:20 AM
I usually follow reference design.
As @mnpebm said, there is no simple answer. It really depends on design e.g. there may be difference if you have two memory chips (one on top, one on bottom on top of each other) vs only one chip etc. But, if you are not sure, 1 cap per pin is fine (I would do the same).
As @mnpebm said, there is no simple answer. It really depends on design e.g. there may be difference if you have two memory chips (one on top, one on bottom on top of each other) vs only one chip etc. But, if you are not sure, 1 cap per pin is fine (I would do the same).
Hung , 05-29-2020, 11:41 AM
thank for Robert, mnpebm.
chitransh92 , 05-30-2020, 11:55 AM
Hello,
Power Distribution Network(PDN) Design is a area of PCB design which deals with this question in detail.
Primarily the decoupling capacitors are selected based on the allowable ripple content for a particular IC like DDR3/4/5 Ram modules etc..
This also depends on Power plane inductance which in turn is a function of Layer stackup.
Placement of decoupling caps is also very important for these high speeds since a couple of nH could hamper the operation.
Reference design is good place to start and important thing to keep in mind is the layer stack of the reference design.
if you are using the decoupling caps same as in the reference design ensure that layer stack also is also similar to it.
Thank you.
Power Distribution Network(PDN) Design is a area of PCB design which deals with this question in detail.
Primarily the decoupling capacitors are selected based on the allowable ripple content for a particular IC like DDR3/4/5 Ram modules etc..
This also depends on Power plane inductance which in turn is a function of Layer stackup.
Placement of decoupling caps is also very important for these high speeds since a couple of nH could hamper the operation.
Reference design is good place to start and important thing to keep in mind is the layer stack of the reference design.
if you are using the decoupling caps same as in the reference design ensure that layer stack also is also similar to it.
Thank you.
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