USE DISCOUNT CODEEXPERT30TO SAVE $30 USD
Microvias above buried vias, ddr3 footprints, copper removal in through vias
Alex Shuklin , 09-09-2020, 02:05 AM
Hi all!
I decided to combine 3 questions in one thread to not create different threads.
1) I've read some article about sometimes it is a problem to place microvias and buried vias above or next to each other in the adjacent layers, because it can cause problems during manufacturing (copper stick out a little bit from the layer and possibly these vias can deform pcb or make a short-circut). Is that true? Do I need to think about that in the PCB design? And when can I do it, or I can't? I see it's done sometimes in the openRex module, so maybe that's not a big issue, since it works.
2) in openRex module there's DDR3 footprint silk is much wider than DDR3 chip itself. Why? Is it just replacement for older memory which was bigger?
3) in Advanced PCB Layout course there's interesting topic: in the through hole vias copper is removed from layers which are not connected to that vias. I looked into gerber files, and looks like Altium create gerbers without copper in that places. Is it very common? I mean, mostly I use KiCad and it doesn't do that. Is it good idea to write a bug report about this topic to KiCad team?
Many thanks.
I decided to combine 3 questions in one thread to not create different threads.
1) I've read some article about sometimes it is a problem to place microvias and buried vias above or next to each other in the adjacent layers, because it can cause problems during manufacturing (copper stick out a little bit from the layer and possibly these vias can deform pcb or make a short-circut). Is that true? Do I need to think about that in the PCB design? And when can I do it, or I can't? I see it's done sometimes in the openRex module, so maybe that's not a big issue, since it works.
2) in openRex module there's DDR3 footprint silk is much wider than DDR3 chip itself. Why? Is it just replacement for older memory which was bigger?
3) in Advanced PCB Layout course there's interesting topic: in the through hole vias copper is removed from layers which are not connected to that vias. I looked into gerber files, and looks like Altium create gerbers without copper in that places. Is it very common? I mean, mostly I use KiCad and it doesn't do that. Is it good idea to write a bug report about this topic to KiCad team?
Many thanks.
robertferanec , 09-12-2020, 02:54 AM
Alex, I guess, you are talking about iMX6 Rex module, not OpenRex (OpenRex is a different board, just through hole vias)
1) Please, could you post a screenshot where it is done? We do not place uVIAs on the top of buried VIAs, it should not be there
2) Yes, the space is for an alternative memory chip with a much bigger size
3) Yes, the unconnected pads are often removed during PCB manufacturing. The CAD system doesn't have to do it, your PCB manufacturer will do it (at least, that is what I was told)
1) Please, could you post a screenshot where it is done? We do not place uVIAs on the top of buried VIAs, it should not be there
2) Yes, the space is for an alternative memory chip with a much bigger size
3) Yes, the unconnected pads are often removed during PCB manufacturing. The CAD system doesn't have to do it, your PCB manufacturer will do it (at least, that is what I was told)
qdrives , 09-12-2020, 07:05 AM
Regarding point 1: it is the reliability of the board. The thermal expansion difference between copper and FR4. There is plenty of information that stacked uvia more then 2 layers will reduce the reliability.The solution is to stagger them, as @robertferanec often does.
Alex Shuklin , 09-14-2020, 03:14 AM
Yes, I made a mistake - that's iMX6 Rex module
Hi that's mostly uvia (L1 -> L2) and burried via (L3-L10). You can see in the screenshots below. Almost all of them are below iMX6 processor (you can find them by pads in the pictures) and one is near R62. One I found is touching or very near in the bottom side. That's near to C174
Hi that's mostly uvia (L1 -> L2) and burried via (L3-L10). You can see in the screenshots below. Almost all of them are below iMX6 processor (you can find them by pads in the pictures) and one is near R62. One I found is touching or very near in the bottom side. That's near to C174
Alex Shuklin , 09-14-2020, 03:23 AM
Can it be that Altium 2020 changed that rule already? I made a simple 6 layers board with one through via to check it. And 2 polygons in the inner layers. Then I created gerbers and looked inside. I found that copper is removed from that via in the layer which is not connected to it.
robertferanec , 09-14-2020, 03:48 AM
Hi that's mostly uvia (L1 -> L2) and burried via (L3-L10).
robertferanec , 09-14-2020, 03:49 AM
Can it be that Altium 2020 changed that rule already?
Alex Shuklin , 09-14-2020, 04:32 AM
Sorry, that's what I tried to ask 
I read an article that it possible can be a problem. And I'm not really sure if it is very important. As far as I remember that was the main opinion: when uVia (L1->L2) is manufactured, the copper "sticking out" a little bit and make distance between L2 and L3 smaller, and same with burried via (L3->L10), so when you have one via above another one, it can be much thinner insulation between them. Should I think about that during layout, or usually it's not too important?
I read an article that it possible can be a problem. And I'm not really sure if it is very important. As far as I remember that was the main opinion: when uVia (L1->L2) is manufactured, the copper "sticking out" a little bit and make distance between L2 and L3 smaller, and same with burried via (L3->L10), so when you have one via above another one, it can be much thinner insulation between them. Should I think about that during layout, or usually it's not too important?
robertferanec , 09-14-2020, 07:15 AM
I have never seen any problems with it ... I believe, PCB manufacturer may fill up the buried vias so resin (the isolation) doesn't flow inside and in that case I do not think that the isolation would be thinner. But I am not expert for this.
qdrives , 09-14-2020, 11:57 AM
I tried to find a more specific link but could not find it fast. Anyway, here is a link to via reliability https://www.smtnet.com/library/files...eliability.pdf
robertferanec , 09-15-2020, 08:42 AM
@qdrives very nice document. Thank you for sharing
Use our interactive Discord forum to reply or ask new questions.