FEDEVEL
Platform forum

rajat_jain_785 , 11-20-2020, 10:18 AM

Hello,

Please find the snapshot from the PCB Board of one of the development boards available from TI attached.

There is a VIA on top of a PAD. Is this acceptable to put Via on top of PAD like the way TI has done it

Regards
RAJAT

qdrives , 11-20-2020, 12:17 PM

No, a standard will cause assembly reliability issues as the solder will go down the via. However, TI may have used it with filled or capped via's, but that adds cost.

Steve.Picotest , 11-20-2020, 01:19 PM

This is common for minimum inductance, we do it pretty frequently, though we do know it can cause issues if we aren't careful. If the chip is big enough we prefer to put the vias inside the pad dimensions rather than in the pad, but for smaller chips we can't do that. The flip side is you have to double the number of capacitors.

robertferanec , 11-21-2020, 12:20 AM

@rajat_jain_785 I just would like to add ... Some time ago I mage this video, maybe it can help: Using VIA in PAD? What you need to know - Guidelines, dimensions and more ... https://youtu.be/FM3pRM0CxGw

, 11-27-2020, 04:47 AM

Hi sir i watched your video iwill be very helpfull to me and I have small request can you send that DFM JUNE 19 REPORT, please

robertferanec , 11-28-2020, 02:00 AM

I attached the DFM File for PCB manufacturing at Exception PCB. Here it is.