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Fine pitch BGA routing
Mohan , 04-30-2021, 08:47 AM
Hello,
I am using the 109 WLP version of MAX32666 in my design. The pitch of this IC is 0.35 mm and I am having a hard time doing the BGA fanout. Is there any fanout examples for a 109 WLP IC with 0.35 mm pitch I can use as reference? What is the recommended layer count, via size, track width and spacing for this density? Please help me out. I am attaching the datasheet and the package outline incase the link does not work.
Thanks & Regards
Mohan Prabhakar
I am using the 109 WLP version of MAX32666 in my design. The pitch of this IC is 0.35 mm and I am having a hard time doing the BGA fanout. Is there any fanout examples for a 109 WLP IC with 0.35 mm pitch I can use as reference? What is the recommended layer count, via size, track width and spacing for this density? Please help me out. I am attaching the datasheet and the package outline incase the link does not work.
Thanks & Regards
Mohan Prabhakar
Mohan , 05-03-2021, 02:18 AM
Dear Robert,
We did come across this app note. Currently we are following the guidelines provided by this. We are still getting stuck. We are trying to route it on a 6 layered board. The stackup we are currently using is
Top
GND
Signal
Signal
GND
Bottom
Unfortunately we are going to have to route in the 2nd layer (GND) to fan out all the pins. So is there any other alternatives?
We did come across this app note. Currently we are following the guidelines provided by this. We are still getting stuck. We are trying to route it on a 6 layered board. The stackup we are currently using is
Top
GND
Signal
Signal
GND
Bottom
Unfortunately we are going to have to route in the 2nd layer (GND) to fan out all the pins. So is there any other alternatives?
robertferanec , 05-03-2021, 03:02 AM
I do not think there are many options - maybe stacked vias could help? But I have not used them yet - I am not sure how reliable and expensive they are.
Mohan , 05-03-2021, 03:08 AM
Yeah, we are trying to figure that out currently. Stacked vias are known to be quite expensive and not highly reliable in my opinion, so we are trying to avoid that. Will keep you posted on how it goes. Looks like routing on layer 2 is the best option we have now.
Mohan , 05-20-2021, 09:43 AM
We decided to use a bigger package of the IC since we were not able to get solid reference for all the signals. We sent it to a few fabricators and they all quoted about USD 3800 for 10 pieces. So we are trying to optimize on the via structures. Whare are some cost-effective via structures in your opinion? Currently we are thinking of doing it with 1-3 , 3-4 , 4-6 and 1-6 vias. Is this a cost effective structure?
robertferanec , 05-24-2021, 02:16 AM
That seems to me like the price what we often see for this kind of PCBs for prototypes. I am not sure how big the PCB is, but if it is small (e.g. 40 x 40mm), then for mass production the price may be very different e.g. 20USD/pcs. The best would be if you also ask for price for mass production, you may find out it may be acceptable.
Mohan , 05-27-2021, 07:17 AM
At high voumes. the price was significanttly lower. It was about USD7/piece. But we wanted to test first. So for now we increased the board size made an easy to manufacture design. Hopefully, this will give us better economics in lower quantities.
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