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Soldermask vs Non-Solder Mask Defined BGA Pads: Rules/compromises?
t12 , 11-20-2023, 04:38 AM
There seems to be quite little online consensus regarding how to best achieve Non Solder Mask Defined (NSMD) pad openings
While there is a fair bit of discussion regarding the pros and cons of both which make perfect sense. Most applications (especially for >= 0.5mm ball pitch) recommend NSMD openings.
However, there is a lot of inconsistency with datasheet recommendations and recommended layouts and reference designs.
For example, for some WL-CSP regulators, they recommend NSMD, but then their layout uses large copper polygons for ground and Vin, effectively creating large SMD openings often irregular in shape, mixed with NSMD openings for feedback pins which have small traces going into them.
In the above case, is it better to link pads with thick traces to limit the effective pad size? (see a TI recommendation below) And this brings up the question, what is the maximum recommended trace width to pad size ratio?
One TI application note (can't seem to find it anymore) had feedback from a fabricator who states that the trace width should not exceed the pad diameter. Is 1:1 acceptable, or do people stick to 70-80% ratio? The same questions goes for the dog bone connection of power pins on FPGAs, connecting the pin pad to via.
I have not seen any advocates for manually reducing individual package pin solder mask openings to account for if they are over a polygon, and there is no information on what scale reduction might need to be applied for the solder bump to have the same height as a NSMD pad.
Via in pad is an expensive solution, but does not address the query.
Finally, how much affect do uneven pad sizes have on reliability and manufacturability?
While there is a fair bit of discussion regarding the pros and cons of both which make perfect sense. Most applications (especially for >= 0.5mm ball pitch) recommend NSMD openings.
However, there is a lot of inconsistency with datasheet recommendations and recommended layouts and reference designs.
For example, for some WL-CSP regulators, they recommend NSMD, but then their layout uses large copper polygons for ground and Vin, effectively creating large SMD openings often irregular in shape, mixed with NSMD openings for feedback pins which have small traces going into them.
In the above case, is it better to link pads with thick traces to limit the effective pad size? (see a TI recommendation below) And this brings up the question, what is the maximum recommended trace width to pad size ratio?
One TI application note (can't seem to find it anymore) had feedback from a fabricator who states that the trace width should not exceed the pad diameter. Is 1:1 acceptable, or do people stick to 70-80% ratio? The same questions goes for the dog bone connection of power pins on FPGAs, connecting the pin pad to via.
I have not seen any advocates for manually reducing individual package pin solder mask openings to account for if they are over a polygon, and there is no information on what scale reduction might need to be applied for the solder bump to have the same height as a NSMD pad.
Via in pad is an expensive solution, but does not address the query.
Finally, how much affect do uneven pad sizes have on reliability and manufacturability?
qdrives , 11-20-2023, 02:32 PM
All good questions. Unfortunately I am not able to answer them (correctly) as I am struggling with the same issues.
However, here is one bit that may help: https://youtu.be/cMxXea16Hxc?t=4795
Secondly, I believe that a lot of fabricators and assemblers are inexperienced when it comes to SMD. In the past components did not need it and the production tolerances were to big.
However, here is one bit that may help: https://youtu.be/cMxXea16Hxc?t=4795
Secondly, I believe that a lot of fabricators and assemblers are inexperienced when it comes to SMD. In the past components did not need it and the production tolerances were to big.
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