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IMR , 06-01-2016, 01:23 AM

Hi, is there any particular disadvantage other than cost with using a via in pad for a BGA package? In figure 5-10 on page 327 of Xilinx 7 Series GTP Transceivers User Guide a via in pad is recommended. If I have to do this for only four caps (GTP power suplies) should I use this method for the other FPGA power supplies (VCCINT, VCCBRAM, VCCAUX, VCCIO) as I will already be paying for the process/setup?

mairomaster , 06-01-2016, 01:30 AM

For the power rails I would still use TH vias if I have the space, since they provide lower inductance to ground/power and also stitch the different ground layers together, which is good for high-speed design. However, if you feel you need to use micro vias just because of this recommendation, you might consider ignoring it and using TH vias all the way, assuming you don't run the transceivers at super high frequencies. I've done design with transceivers running at 2.5 GHz and everything works fine on all TH vias board.

robertferanec , 06-01-2016, 01:48 AM

I agree with @mairomaster. Also, we used VIAs in pad some time ago and we had problems during assembly. Since then I do not use VIAs in pads.

BTW: do they recommend to use VIA in pad for powers? Please could you attach a link to the user file? I am curious.

IMR , 06-01-2016, 01:55 AM

The manufacture that I want to use has a 4:1 aspect ratio for drill holes. So a TH via will be 0.4mm on a 1.6mm board. Do you think I should use a buried via as the hole diameter will be reduced to 0.15mm?

IMR , 06-01-2016, 02:03 AM

No they specify that the decoupling for the other supplies must be placed within 2 inches of the point of load on page 23 under bulk capacitors.

IMR , 06-01-2016, 02:05 AM

Didn't realise your add link tool doesn't work.

[1] http://www.xilinx.com/support/docume...ansceivers.pdf recommendation for vias in pads on page 327 for MGTAVCC and MGTAVTT supplies only.
[2] http://www.xilinx.com/support/docume...Series_PCB.pdf recomendation for caps to be placed within two inches of the point of load on page 23 for other supplies.

IMR , 06-01-2016, 02:30 AM

Ok I think I will do vias in pads for GTP transceivers only and the other supplies will use buried vias due to space limitations.

mairomaster , 06-01-2016, 03:35 AM

^^ The document has less than 327 pages. The only information about via in pad that I find with the search was saying that you need to use such to fit 0402 capacitors. However, they provide the option to use 0201 capacitors with TH vias as well, which might be the better and cheaper option, but you need to speak to your manufacturer as well.

4:1 ratio for TH vias sounds very bad to me. Are you sure your manufacturer can meet the desired requirements for the board? I can't imagine how can they make filled micro vias, but can't make TH vias with better ration (1:10 at least).

robertferanec , 06-01-2016, 04:32 AM

I agree about the 4:1, it doesnt look right to me. Is not that for uVIAs / Blind VIAs?

robertferanec , 06-01-2016, 04:42 AM

@mairomaster is right, the attached document doesnt have so many pages, you probably meant to say 237. It says:

Filled VIAs are something else - you put something inside them. From the explanation they just don't want solder to flow inside the VIA. Have a look here for explanation about VIA types: http://www.pcbuniverse.com/pcbu-tech-tips.php?a=5

"Non-Conductive Fill: A common misconception is that a non-conductive fill will either not pass any or only a very weak electrical signal through the via. This is not true. The barrels of the vias will still be plated with copper the same as any other via on the board, the only difference is the empty air in barrel is replaced with the fill material. This is usually done to prevent solder or other contaminants from entering the via or provide structural support for a copper pad covering the open hole in the case of a Via In Pad. Non-Conductive fill is another term for mask plugged vias."

I normally just mask VIAs under the BGA and it is ok.

mairomaster , 06-01-2016, 05:35 AM

I don't think the manufacturer makes any holes. The via diameters are normally small and because of the surface tension the mask shouldn't flow too deep in the via hole, maybe just a little bit. Closing the air inside in such cases is not a big problem, if it expands it will just slightly crack the solder mask over the via so it can escape. That is what I know from experience and speaking to manufacturers. I am not 100% sure about it though.

As I explained above, it only could be a problem with vias in pad, since you have the solder over the via, hence the air expansion can crack the solder joint above.

EDIT: Hmm this multiple stacking of quotes still doesn't work for me, or I am doing something wrong.

robertferanec , 06-01-2016, 05:44 AM

The air caught in VIAs in PADS .. that is exactly the problem we had with assembly when we used VIAs in pads. I have also heard about possible problems with air caught inside VIAs filled from both sides - but have not see it (we have never used that technology).

PS: it really looks like quote in quote doesnt work(?). I will have a look

IMR , 06-02-2016, 03:43 AM

If I place my decoupling like this would this be poor choice? In the attached image the power supply has decoupling near the power supply but is not drawn, the black squares are VCC capacitor pads, the black circles are FPGA pins attached to VCC, the circles are vias and the hatched squares are the capacitor pads attached to ground. As the FPGA pin vias are closer to the power supply will current flow from the power supply directly to the FPGA pin vias and bypass the decoupling? (effectively removing the filtering which is not what I want)

robertferanec , 06-02-2016, 08:35 AM

It's not an easy topic. @IMR, I see you have Advanced PCB Layout Course. Have a look at the Lesson 2. That should help you.

IMR , 06-02-2016, 09:42 AM

Am I thinking about this the right way conceptually? In Figure 12. of the following document the poor via placement cause the current to flow from the power supply from the IC. When this happens there is no filtering? So I need to design in such a way that the current is forced to move through the capacitor?

[1] http://www.ti.com.cn/cn/lit/an/scaa082/scaa082.pdf

mairomaster , 06-02-2016, 10:48 AM

Yes, you are thinking the right way. However, it is not so bad in every case. In your drawing from your previous post, it might be OK if: you place the capacitors as close as possible to the IC, those are large value capacitors (>= 10 uF lets say) and you don't have pins which are very far away from the capacitors.
It is more crucial with small capacitors (< 100 nF for example) which need to be as close as possible to the pins they decouple (in order to reduce the inductance). Such capacitors normally you want to put directly under the particular pins.

robertferanec , 06-03-2016, 12:20 AM

Yes, I always try to place the capacitors the way, that the current will flow through them or from them. @mairomaster's answer is a nice one 1+