| FORUM

FEDEVEL
Platform forum

USE DISCOUNT CODE
EXPERT30
TO SAVE $30 USD

Forum / Schematic Design & PCB Layout / Splitting Address / Control Signals to different layers

Splitting Address / Control Signals to different layers

Geato , 11-06-2015, 10:43 AM

I am trying to apply my skills I learned in your course. I am having an issue because I am not using micro-vias due to cost reasons. I am having difficulty with the breakout of the address / control lines. I am using a i.MX6SoloX 400 BGA. The signal that always gets me is the DRAM_ODTO. It forces me to route the lines back into the BGA which extends the length and that makes it impossible to length match the short runs. You can see the 9 lines I have had to unrout in the picture. I recall you said to keep all the signals within a group on the same layers but have you ever had problems breaking the group into 2 different layers? I am only using 2 DDR3's on an 8 layer stack.

robertferanec , 11-09-2015, 01:04 AM

Hello Geato. Maybe try to fanout CPU first. After you have all the pins out of the CPU, then connect them to the memory chips.

Here are some screenshots from our new open source project using iMX6, 8 layer PCB and through hole VIAs only. Our layout has not been finished yet, but I hope it helps you (we use fly-by, so it looks a little bit different than T-branch, but fanout under CPU would be the same).