Striplines with discontinuous reference planes
noeliascotti@gmail.com , 09-26-2017, 05:44 AM
Hello, I am routing one LPDDR3 to an imx7 controller. The imx7 I am using is the 0.4 mm BGA, so, it is too difficult to fanout the signals.
You can see on the attachment that the red power plane (top layer) and the yellow power plane (L2) aren't good power planes because there are tracks on that layers, so, the striplines on L2 and L3 have horrible references.
I can't simulate this situation with Hyperlynx because Hyperlynx assumes that the power planes are perfect. If I consider perfect planes the characteristic impedances are fine (50 ohm). If I consider no power planes the characteristic impedances are out of range (70 ohm). So, I don't know the real impedances and I can't simulate these signals properly.
What can I do? Is it too severe? I think there is no way to do it better with 2+N+2.
I am using 0.1/0.25 mm microvias and 0.15/0.40 mm buried vias.
Thanks!
You can see on the attachment that the red power plane (top layer) and the yellow power plane (L2) aren't good power planes because there are tracks on that layers, so, the striplines on L2 and L3 have horrible references.
I can't simulate this situation with Hyperlynx because Hyperlynx assumes that the power planes are perfect. If I consider perfect planes the characteristic impedances are fine (50 ohm). If I consider no power planes the characteristic impedances are out of range (70 ohm). So, I don't know the real impedances and I can't simulate these signals properly.
What can I do? Is it too severe? I think there is no way to do it better with 2+N+2.
I am using 0.1/0.25 mm microvias and 0.15/0.40 mm buried vias.
Thanks!
robertferanec , 09-27-2017, 09:20 AM
@noeliascotti@gmail.com please, would it be possible to reload the attachment? I think it has not been properly uploaded and I can not see anything there.
noeliascotti@gmail.com , 09-27-2017, 10:16 AM
I have uploaded the attachment again!
robertferanec , 09-27-2017, 11:29 AM
This looks quite difficult layout. How they do it in reference layout?
noeliascotti@gmail.com , 09-27-2017, 11:56 AM
Sorry, I don't understand the question...
robertferanec , 09-27-2017, 12:21 PM
Does the manufacturer has iMX7 reference board with this chip? If yes, they should be able to give you the layout files, so you can see what stackup they used and how they did the fanout and layout. So you can use the same technique.
noeliascotti@gmail.com , 09-28-2017, 10:22 AM
I have no details about the stackup, but I saw the design (WARP7 board) with the Allegro Viewer and they use 10 layers and 3 levels of microvias (3+N+3). This board is more expensive that mine, I use 2 levels of microvias.
The Warp board has the same problem that mine, has transmision lines without reference in some parts.
I think that the clue is on the simulation software. Perhaps with a 3D field solver, the accuracy is better and the simulation results are reliable. My Hyperlynx version is a 2.5D field solver.
Today I could enable the trace to area fill coupling, in order to obtain more reliable impedance calculations, but it would be better to have a 3D Field Solver.
What do you think? Is it a risky PCB? Is it too severe a 33 mm stripline without reference plane in a 5 mm segment?
Thanks for your help.
The Warp board has the same problem that mine, has transmision lines without reference in some parts.
I think that the clue is on the simulation software. Perhaps with a 3D field solver, the accuracy is better and the simulation results are reliable. My Hyperlynx version is a 2.5D field solver.
Today I could enable the trace to area fill coupling, in order to obtain more reliable impedance calculations, but it would be better to have a 3D Field Solver.
What do you think? Is it a risky PCB? Is it too severe a 33 mm stripline without reference plane in a 5 mm segment?
Thanks for your help.
mairomaster , 09-29-2017, 01:44 AM
I've had big signal integrity problems with LPDDR3 before, while having much better layout (with perfect planes, etc.). I wouldn't risk doing it the way you describe without consulting with NXP first, if possible. I would guess they will recommend you following their example design anyway.
robertferanec , 09-29-2017, 08:06 AM
I agree with @mairomaster.
It is very hard to say just from picture what could be the solution. Maybe, when they used so small pitch, that could be the reason why they had to go for 3+N+3? Using small chips makes the PCB more expensive.
I am not expert in simulations, but we did have board which passed simulations perfectly and the real memory interface was failing occasionally. So, even if your simulation results will be ok, for this kind of layout (multiple tracks over each other on multiple layers without close reference plane), I am not sure how much I would rely on the results.
The thing is, your tracks are very short and it looks to me, they only go to one footprint. So, maybe this also plays role and maybe that gives you some advantage (so even imperfectly routed tracks still can work oki). However, would I risk it? I do not know. Especially if this is a very first prototype, I would probably try to design it based on the reference board - so you can be sure, that your first prototype works oki and you can use it for further development (e.g. software, enclosure, applications, ....). If everything works oki, and you would need to optimize the cost, than maybe later I would try to experiment and I would try to move it to cheaper PCB ... but I would definitely pointed out to my boss, that it is the area where even NXP didn't go.
It is very hard to say just from picture what could be the solution. Maybe, when they used so small pitch, that could be the reason why they had to go for 3+N+3? Using small chips makes the PCB more expensive.
I am not expert in simulations, but we did have board which passed simulations perfectly and the real memory interface was failing occasionally. So, even if your simulation results will be ok, for this kind of layout (multiple tracks over each other on multiple layers without close reference plane), I am not sure how much I would rely on the results.
The thing is, your tracks are very short and it looks to me, they only go to one footprint. So, maybe this also plays role and maybe that gives you some advantage (so even imperfectly routed tracks still can work oki). However, would I risk it? I do not know. Especially if this is a very first prototype, I would probably try to design it based on the reference board - so you can be sure, that your first prototype works oki and you can use it for further development (e.g. software, enclosure, applications, ....). If everything works oki, and you would need to optimize the cost, than maybe later I would try to experiment and I would try to move it to cheaper PCB ... but I would definitely pointed out to my boss, that it is the area where even NXP didn't go.
noeliascotti@gmail.com , 09-29-2017, 05:24 PM
Thanks for your help. I will speak with my pcb manufacturer in order to start again with 3+N+3 
In the reference design there are also tracks and segments without reference, but I think it is better than mine.
Thanks!
In the reference design there are also tracks and segments without reference, but I think it is better than mine.
Thanks!
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