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, 07-13-2026, 09:47 AM

I am a student sir and learned from your youtube videos and made a pcb design and ordered from jlcpcb with component placement but after delivering i checked with multimeter with shots and continuity everything is correct but not working

, 07-13-2026, 09:53 AM

🤖 In the meantime, here’s a response from the [FEDEVEL AI HW Assistant]().
It helps to find relevant resources for your question, but it may make mistakes as it’s still in early development.

This is the response from the AI Assistant:
Here are key areas to investigate based on common PCB layout mistakes covered in our videos:

1. **Noisy Signal Cross-Talk**
Even with good continuity, high-speed signals (like clock lines or switching power traces) routed too close to sensitive analog traces can cause interference. Check if your layout separates noisy and sensitive signals as shown in this [PCB review example](https://www.youtube.com/watch?v=tlLDUFhaboo&t=6).

2. **Power Delivery Issues**
Continuity checks don't reveal voltage drops or insufficient current capacity:
- Verify power traces/polygons are wide enough for your current (e.g., 5A needs ~2mm width for 1oz copper)
- Check decoupling capacitors are placed _directly_ at IC power pins ([example](https://www.youtube.com/watch?v=-luLIJqURlY&t=1569))

3. **Impedance Mismatches**
Critical for USB/differential pairs. Even short traces need controlled impedance. JLCPCB requires 3.5mil spacing for 4-layer boards - did you [verify your stackup](https://www.youtube.com/watch?v=-luLIJqURlY&t=2498)?

4. **Component Rotation Errors**
Double-check pick-and-place files against actual assembly. JLCPCB sometimes adjusts rotations - did you [confirm their placement report](https://www.youtube.com/watch?v=yptbPYe1BL0&t=5516)?

5. **Hidden DRC Violations**
Run full Design Rule Check (DRC) including:
- Differential pair length matching ([common error](https://www.youtube.com/watch?v=-luLIJqURlY&t=3266))
- Component clearance (min 0.1mm for JLCPCB)

**Next Steps:**
1. Power up the board and check voltages at _all_ IC pins (not just power entry)
2.

, 07-13-2026, 09:53 AM

Use oscilloscope to check clock signals/switching nodes
3. Verify component polarities (diodes, caps) match PCB silkscreen
4. Reflow suspicious joints with hot air (cold solder joints pass continuity but fail under load)

Need more specific help? Share:
- Screenshot of critical signal routing
- Power section layout
- DRC report summary

This approach helped debug a similar student project where a [0.5mm misplaced capacitor](https://www.youtube.com/watch?v=hmD4EtEF2sQ&t=1081) caused regulator instability.

You can continue chatting with the AI Assistant here:
https://fedevel.com/hw-assistant

, 07-13-2026, 01:00 PM

PL HELP ANYONE

QDrives , 07-13-2026, 02:17 PM

Next time spend more time on the 'style' - as in make it readable.
Yellow boxes - text overlaps
Violet arrows - a dot comes when 3 or more connections join. However, the arrows point to just 2 connections, so something is not entirely correct.
Green box - net names below the net?
Red arrow - your first problem.

QDrives , 07-13-2026, 02:18 PM

Your usb connector needs to move out of the board more.

Robert Feranec , 07-14-2026, 12:25 AM

what is not working?

QDrives , 07-14-2026, 01:37 PM

Board not working