ATHONOR , 11-22-2023, 09:20 PM
Hi I am working on a project which based around a the SanCloud BeagleBone Enhanced (started before I was involved).Looking at the SanCloud Design, they have used 2 x 8-bit DDR3 ICs in mirror configuration to achieve 16-bit 1GB RAM. From what I can gather, due to using two IC's they have included VTT termination to improve signal integrity.Now for production, it is not ideal to put both DRAM IC's on either side of the board - and we are opting for the single-sided DRAM placement. I have noticed that the SanCloud does not terminate the DDR3 clock signals. Reviewing the Artwork, I believe they have not terminated CLK signals because they have used T-branch routing for the clocks (Via'd up in the middle of the mirrored ICs, and then routed out from the via to both IC balls in a T, as CLK pin is in the middle row balls, hence a short distance) - See poorly attached drawing.So my question is.. they haven't termianted CLK signals. I assume this is because the T-branch is effectively the same as point-to-point, and with such little distance can get away with it. However, for my design where two IC's will be some distance away - I will also need to include the termination for CLK signals? https://github.com/SanCloudLtd/BeagleBoneEnhanced/blob/master/V1G/SanCloud_BeagleBone_Enhanced_1G.PDF (Schematic - DDR3 page 9)https://www.ti.com/lit/ds/symlink/am3358.pdf (Texas Instruments CPU Datasheet - DDR3 Clock Termination page 181)https://github.com/beagleboard/BeagleBoneEnhanced/blob/master/SanCloud_BeagleBone_Enhanced_1E_Final%20Artwork%20Prints.PDF (Artwork for SanCloud design)