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FPGA, clock/inductor problem
corlas , 07-11-2024, 05:54 PM
Hello, I am designing an ultra-small electronic system and I have one problem. I need to place the PMIC for the FPGA near the FPGA board. The inductor is really close to the master FPGA clock 50MHz (1-2mm). Can the inductor negatively affect the signal?
QDrives , 07-11-2024, 08:24 PM
- Outer layer for the clock?- (Fully) Shielded inductor?- How critical is clock jitter for your application?However, if it is possible, even if it takes same hours redoing the layout, I would move it to >5mm
corlas , 07-12-2024, 05:56 AM
The clock signal is routed mostly on the inner layer, but the oscillator is right next to the inductor. Here is the inductor link https://www2.mouser.com/ProductDetail/Coilcraft/XFL4030-202MEC?qs=chTDxNqvsylyJCa7i2HKuA%3D%3D&_gl=1*2v9y2u*_ga*NTUyMjkzMDczLjE3MjA3NjM1MDE.*_ga_15W4STQT4T*MTcyMDc2MzUwMS4xLjEuMTcyMDc2MzUxMi40OS4wLjAwell, the clock is the main FPGA clock so I think the clock jitter is pretty critical.
QDrives , 07-12-2024, 10:03 PM
The inductor is only 3mm high, so traces and other components on the adapter board or also <= 3mm from the oscillator.So the whole layout in that area is critical. I do not know if the inductor would be the worst thing (as it is a shielded inductor with bottom termination).Is the oscillator on the switch node end, output end or 'parallel' to in->out?
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