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Forum / Schematic Design & PCB Layout / JLC 3313 6-Layer stackup with the thin middle prepreg

JLC 3313 6-Layer stackup with the thin middle prepreg

Evans Thomas , 07-09-2026, 08:05 PM

Hello,
I am relatively new to PCB design and this is my first 6 layer board. This is a flight controller with SDMMC, SPI, DSHOT600 signal lines. I have components only on the top but a few solder pads on the bottom. I want to know if a SIG/GND/SIG/PWR/GND/SIG is acceptable with the L3 signals carrying much of the higher speed traces that transitions from the outer layers. I can send project files/images.

, 07-09-2026, 08:13 PM

🤖 In the meantime, here’s a response from the [FEDEVEL AI HW Assistant]().
It helps to find relevant resources for your question, but it may make mistakes as it’s still in early development.

This is the response from the AI Assistant:
The proposed 6-layer stackup **SIG/GND/SIG/PWR/GND/SIG** has potential issues but can be improved with careful implementation. Here's the analysis:

### Key Considerations for High-Speed Signals (SDMMC, SPI, DSHOT600):
1. **Signal Layer Adjacency**:
- Your L3 (signal) adjacent to L4 (power) creates a risk of **crosstalk** and **impedance discontinuities** if the power plane isn't solid. Power planes can act as reference planes *if* they’re stable and well-decoupled, but ground is always preferred for critical signals ([Source 5](https://www.youtube.com/watch?v=52fxuRGifLU&t=2366)).

2. **Return Paths**:
- Signals on L3 (middle layer) will reference either L2 (GND) or L4 (PWR). If referencing the power plane, ensure it’s a **solid copper pour** with ample decoupling capacitors nearby. Broken power planes or gaps will disrupt return paths, causing EMI ([Source 8](https://www.youtube.com/watch?v=60RxCiZuD9E&t=272)).

3. **Thin Prepreg Between Layers**:
- JLC’s 3313 stackup likely places L3 very close to L4. This tight coupling increases capacitance but risks crosstalk if signals on L3 run parallel to noisy power traces on L4. Route L3 signals **orthogonally** to L4 power traces to minimize coupling ([Source 3](https://www.youtube.com/watch?v=BlHLmQ2HO1w&t=3235)).

### Recommended Improvements:
1.

, 07-09-2026, 08:13 PM

**Adjust Layer Order** (if possible):
- A safer 6-layer stackup for high-speed signals:
**SIG/GND/SIG/GND/PWR/SIG**
This places ground planes adjacent to all critical signal layers (L2 and L4), ensuring consistent return paths ([Source 12](https://www.youtube.com/watch?v=ijdzS118hjs&t=14)).

2. **Mitigation for Existing Stackup**:
- Pour **ground copper** on L3 around high-speed traces to stabilize their reference.
- Use **stitching vias** near layer transitions (e.g., L1→L3 or L6→L3) to maintain return current continuity ([Source 15](https://www.youtube.com/watch?v=Lqc1jmbSxnE&t=337)).

3. **Power Plane Management**:
- Make L4 (power) a **solid plane** (no splits) for critical rails (e.g., 3.3V).
- Place decoupling capacitors **directly under ICs** to minimize loop inductance ([Source 9](https://www.youtube.com/watch?v=52fxuRGifLU&t=4119)).

### Example Stackup Success Story:
A similar 6-layer design reduced EMI by 15 dB by using adjacent ground planes and strategic power pours ([Source 10](https://www.youtube.com/watch?v=52fxuRGifLU&t=2869)).

### Final Notes:
- If you’re locked into JLC’s 3313 stackup, focus on **solid power planes** and **ground stitching**.
- Route high-speed signals on L3 perpendicular to adjacent layers.
- Avoid long parallel runs between L3 and L4.

For a full design review, share your layer stackup distances and critical signal routing.

You can continue chatting with the AI Assistant here:
https://fedevel.com/hw-assistant

Evans Thomas , 07-10-2026, 09:19 AM

I dont have traces on L4. Only power pours

Skoomadentist , 07-10-2026, 10:21 AM

You’ll need a stitching capacitor every time a signal changes reference plane from gnd to pwr and vice versa. IOW any time a signal changes to L3 in your stackup.
Afaik you also risk warping as your stackup is no longer symmetric due to pwr plane. If you mean L4 is power _routes_ instead of plane, you’re going to have problems due to coupling between L3 and L4 routes and long distance from L3 to L2 reference plane.

Skoomadentist , 07-10-2026, 10:24 AM

Personally I’d consider the recently added slightly more economic L1/L2/L3 - L4/L5/L6 stackup (3313E) that doesn’t cost a fortune like previous such stackups if you don’t truly need a power plane and can instead use power routes.

Evans Thomas , 07-10-2026, 02:20 PM

it is a small 38x38 board. I have used a pour for power under all traces on l3 so i do not have split planes.

QDrives , 07-10-2026, 03:03 PM

Just as @Skoomadentist mentioned...
It is **not** just the order (signal, gnd or power), but more importantly, the thickness of the dieletrics between them.

If you have thick cores (L2-L3 and L4-L5) and thin prepreg (L1-L2, L3-L4, L5-L6) then signals on L3 will reference power on L4 more Gnd on L2.
An alternative would be to have thin cores (max 0.2mm) and a thick dielectric between L3 and L4 (sometimes called a fake 8 layer) then your signal uses L2 Gnd more for the reference.

Evans Thomas , 07-10-2026, 04:28 PM

Yeah, but my probelm is I want to use thsi stackup which will save a lot of money

Skoomadentist , 07-10-2026, 04:45 PM

Then you should use sig+pwr - gnd - gnd - sig+pwr - gnd - sig+pwr. A lone power plane with that stackup is electrically pointless and its only real use is making power routing slightly easier.

Skoomadentist , 07-10-2026, 04:47 PM

Most texts don't emphasize it enough that a power plane only provides meaningful distributed capacitance if it has an immediately adjacent ground plane next to it with only a thin core in between (0.1 mm or at most 0.2 mm).

Skoomadentist , 07-10-2026, 04:50 PM

Even with 0.1 mm distance, 38x38mm isn't much area, so the impedance of the distributed capacitance only decreases below decoupling caps' impedance after 300 MHz or so. With your stackup any distributed capacitance would be less than 100 pF and thus pointless.

Evans Thomas , 07-10-2026, 04:50 PM

But it has to be that 6 layer stackup itself. The reason I went with a 3.3V pour is because else I dont have space to route that power on rthe siognal layers and if I so that on the gnd plane, it will get cut up

Skoomadentist , 07-10-2026, 04:53 PM

Ask yourself: Do you have space for the stitching capacitors that _must_ be placed right next to every place a signal changes from L1 <-> L3 and L3 <-> L6?

Evans Thomas , 07-10-2026, 06:43 PM

So having the gnd on L2 and L5 does nothign?

Skoomadentist , 07-10-2026, 06:49 PM

It does for layers L1 and L6. For L3 and L4 it provides poor reference (for anything high speed or for providing meaningful distributed capacitance).

Evans Thomas , 07-10-2026, 07:06 PM

So it would still be like a layer reference change

Skoomadentist , 07-11-2026, 12:14 PM

With that stackup every L1 <-> L3 <-> L6 change is a reference change, whether you use gnd or pwr for L4. What is important is that putting a ground stitching via right next to the signal via is both electrically better and easier to do (less space taken, less need to clear up other routing) than putting a stitching capacitor.

Evans Thomas , 07-11-2026, 05:16 PM

I have those stitching vias

Evans Thomas , 07-11-2026, 05:17 PM

So would l3 being sandwiched between l2 gnd and l4 pwr still cause problems?

Evans Thomas , 07-11-2026, 05:18 PM

And if so, would you recommend a few SPI and mostly dshot lines on such a layer other than SDMMC? I can send my project files if needed

QDrives , 07-12-2026, 02:17 PM

What are the dielectric thicknesses?
With thick cores, the coupling is much higher to L4 and therefor power in your case.

Evans Thomas , 07-12-2026, 04:54 PM

QDrives , 07-12-2026, 06:16 PM

So thick core and thin prepreg. That means L3 is coupled to L4.
Make L4 Gnd and L5 or L6 power.

Evans Thomas , 07-12-2026, 06:44 PM

I made L5 Sig/Pwr (3.3v) and L6 GND with a few traces but they have gnd pour between.

Evans Thomas , 07-12-2026, 06:46 PM

L3 is also sig/pwr. L4 is mostly gnd underneath the signals on L3

Evans Thomas , 07-12-2026, 06:47 PM

Is that 3.3v pour good? Anywhere its gets too narrow? There's at least 1mm of 0.5oz copper to every 3.3v via as far as I checked

QDrives , 07-13-2026, 02:02 PM

You might want to think about making L5 vertical and L3 horizontal layers. That may give space for the connections on L4 and L6.
Also move some traces to reduce net antennas and have at least 2 vias in a polygon pour.

Evans Thomas , 07-13-2026, 03:21 PM

Well I made L4 and L6 gnd now... I thought bout orhtogonal routing but seems like in this case it seems to be hard. one problem being it will need lots more vias.

Evans Thomas , 07-13-2026, 03:21 PM

I did have 2 vias atleast for power. Do you mean for each 3.3V area from the top layer?

QDrives , 07-13-2026, 06:48 PM

All point to single via copper pours.

QDrives , 07-13-2026, 06:49 PM

That is only a problem if the via gets into conflict with components.

Evans Thomas , 07-13-2026, 07:30 PM

Okay will try to get 2 vias. Another problem is my 3.3v pour will be greatly reduced besides a lot of antipads tearing my planes. I thought I'd avoid that. Hence I managed to route most signls on L3 and it seems like its fine. I'm having 3W spacing

QDrives , 07-13-2026, 09:29 PM

Often it is easier and better to move some traces to group the island.

Evans Thomas , 07-14-2026, 08:29 AM

I have revised stuff @QDrives. Alternating GND as said before. L2 is fully gnd so not shown. Got that pour on L4 on the left. Basically its the input power to a transisotr that is used to switch power to the leftmost fat trace on L3. L5 is power poured and traces are only routed over continuous sectiosn of L6. L6 is GND. Traces on L6 reference pwr. But I have ensured ground completely surrounding them.