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Mahsheed , 05-17-2025, 02:03 PM

Hello,

I am trying to build my custom board for Cyclone V 5CSEBA6 (just like DE10 Nano), but I am unable to find any information about the PCB design guidelines of HPS Peripherals like RAM, HDMI etc. About the routing topology and impedance values of single ended and differential signals. I am litterally confused if I should go for T Topology or Fly By topology etc etc

corlas , 05-17-2025, 03:23 PM

I've designed a PCB with cyclone V FPGA before... The HW documentation is not the best... You should look for that kind of information on intels site and If you're lucky you will find what you need. Maybe this might help: https://www.intel.com/programmable/technical-pdfs/683801.pdf

If its your first design, the best thing is to copy as much as you can from existing designs like: https://www.analog.com/media/en/technical-documentation/eval-board-schematic/c5_soc_devkit_c.pdf

Its not the same FPGA but you can check the differences here: https://www.intel.com/content/www/us/en/content-details/714207/cyclone-v-fpga-and-soc-fpga-product-table.html(

also this might help for the FPGA/SOC quartus pin planning: https://www.intel.com/content/www/us/en/content-details/654271/arria-v-and-cyclone-v-design-guidelines.html

One thing you MUST do after you finish the schematic is to create a quartus project and test if it lets you compile your pinout. If it doesnt compile, there has to be some error in your schematic pinout.

Everything else, I pretty much knew before (High-speed layouts, etc), so I don't know where to look for that on intels side specifically, sorry

corlas , 05-17-2025, 03:23 PM

hope this helps at least a little bit

Mahsheed , 05-17-2025, 10:19 PM

Thank you very much for the response. Yes, indeed, Intel is pretty much silent about the PCB design guidelines. I literally skimmed too many documents and couldn't find any thing.

I have pretty much completed my schematic (my design overlaps with DE10 Nano board, so I had huge help from its schematic). But I am facing following issues related to routing

1) How do I know which routing topology to be used for DDR3 integration with HPS. The document is all about using Soft or Hard IP blocks in FPGA and its integration with EMIF. I want to integrate with HPS side.

2) What impedance values are required for differential signals and single ended. I would need it for DDR3, HDMI and ethernet.

3) Also, although, I just copied from DE10 Nano schematics. But how do we get to know the values and how many decoupling capacitors are needed on the power pins of SoC?

And thankyou for pointing out the Quartus pin mapping scenario. I skipped that part. I would add all the details in a quartus project and see if it allows me to use those pins as needed or not. Although, my main peripherals are with the HPS side, and from FPGA side, I am just taking the GPIOs out as serial outputs, so it shouldn't be a problem, but I would confirm it as well.

corlas , 05-17-2025, 11:31 PM

1) I didn't design that many DDR3 PCBs but I think Fly-by is the best choice. You can learn more about it here for example https://resources.altium.com/p/fly-topology-routing-ddr3-and-ddr4-memory

2) If you can't find this info on intels website, these impedances are defined by the interface itself. For DDR3 It's 40/80 Ohms or 50/100 Ohms but for DDR3 I have always used 50/100 Ohms and it was always ok. This might help: https://hands.com/~lkcl/eoma/rockchip_rk3288/AN3940.pdf
For HDMI and Ethernet, it should be 100R differential impedance.

3) For this, you should use the Altera PDN tool: https://www.intel.com/content/dam/altera-www/global/en_US/others/technology/signal/power-distribution-network/pdn-tool-28nm.zip

Mahsheed , 05-20-2025, 09:23 PM

Thank you so much 🙂