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PN , 12-09-2024, 11:16 AM

Hello everyone.

Is it compulsory to consider the SoC pin package delay when performing delay matching on DDR lines?
Can I ignore the delay without any adverse issue?

Tell me what you guys think based on your experience.

Regards,

Paul.

Robert Feranec , 12-10-2024, 10:57 AM

length in package should be considered in DDR layout

PN , 12-13-2024, 06:40 AM

Thanks for your response, Robert.

Is the length in package for the DDR Chip also to be considered or just the SoC?

PN , 12-13-2024, 06:52 AM

From your experience, what's the best way to specify traces that require controlled impedance to PCB makers?

Robert Feranec , 12-14-2024, 11:23 AM

I believe, DDR chips have length in package matched (but I have not confirmed that). your second question, what do you mean by "specify"? I put a table into manufacturing notes layer with track geometry for each impedance + I attach screenshots with tracks highlighted for specific impedance and for each layer they are routed on.

PN , 12-14-2024, 01:16 PM

I think you pretty much answered my question about communicating control impedance requirement to PCB makers. Thank you very much.

Finally, which tool do you use to highlight your traces of interest?
Do you have a YouTube video on that?

PN , 12-14-2024, 01:18 PM

And by the way, I've been watching your youtube videos, and have learnt a lot from them. Nice Job!

Robert Feranec , 12-14-2024, 04:56 PM

- just screenshots from altium with specific tracks highlighted. I don't have video about this
- Thank you 🙂

QDrives , 12-14-2024, 08:33 PM

One tip I was told is comment like "All traces of 0.12mm on layers 3 and 5, wide should be 40ohm, all traces of 0.1mm on layers 3 and 5 should be 50 ohm".

PN , 12-16-2024, 11:58 PM

Alright. Thank you.

PN , 12-17-2024, 12:09 AM

This helps as well. Thanks.