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Evans Thomas , 07-13-2026, 09:48 AM

So I have a TPS62933 and have the output bulk and the 0.1uF on a zone with the inductor pad on the top layer. I wish to route out the power from another layer. Do I need to put and encompass a via on the 0.1 uF cap on this pwr layer zone or can I just only include vias from near the bulks.

Thanks

, 07-13-2026, 09:53 AM

🤖 In the meantime, here’s a response from the [FEDEVEL AI HW Assistant]().
It helps to find relevant resources for your question, but it may make mistakes as it’s still in early development.

This is the response from the AI Assistant:
For buck converter outputs, both bulk capacitors and high-frequency decoupling caps (like your 0.1μF) need careful via placement. Here's the breakdown:

1. **Key Principle**: Every capacitor should have its own via(s) directly at its pad to minimize loop inductance. This applies to both bulk caps and smaller decoupling caps. Connecting multiple caps through shared vias or planes increases impedance ([Video 1](https://www.youtube.com/watch?v=v8seW2BZits&t=1)).

2. **0.1μF Cap Treatment**:
- The 0.1μF capacitor handles high-frequency ripple - its effectiveness depends on **low-inductance paths**.
- Place at least one via directly at its pad to connect to your power plane. Don't rely on copper pours or distant vias ([Video 8](https://www.youtube.com/watch?v=XumNc480qYo&t=399)).

3. **Bulk Caps**:
- Use multiple vias near bulk caps (quantity depends on current). For example, a 3A output might need 2-3 vias per bulk cap pad ([Video 3](https://www.youtube.com/watch?v=bU2Ef-2ZIK4&t=1870)).

4. **Critical Layout Flow**:
```
Inductor → Bulk caps (multiple vias) → 0.1μF cap (dedicated via) → Power plane
```
Avoid "daisy-chaining" caps through shared copper - each should have direct plane access.

5. **Pro Tip**: Use via-in-pad for the 0.1μF if space allows, but ensure proper annular ring (minimum 0.15mm for reliability) ([Video 4](https://www.youtube.com/watch?v=FM3pRM0CxGw&t=0)).

While bulk caps handle steady-state current, the 0.1μF cap is critical for high-frequency performance - both need optimized via placement. Don't skip vias on the smaller cap!

You can continue chatting with the AI Assistant here:
https://fedevel.com/hw-assistant

QDrives , 07-13-2026, 02:06 PM

Can you provide schematic + layout of this bit?

Evans Thomas , 07-13-2026, 03:16 PM

Should I include the via from the 0.1uf as shown in green layer or doesn't it matter as in blue? Also is the placement for both 0.1uF caps of both bucks correct?

QDrives , 07-13-2026, 06:45 PM

Are you talking about C30 and C31 ? The bootstrap capacitor.
Or C32 and C33? Part of the output bulk capacitance.

You placed vias in pads. For low cost board - do not do that.
The vias need to be filled (and capped) when placed in a via.

Evans Thomas , 07-13-2026, 07:27 PM

Talking about output only - the 2x 22uF and 1x 0.1uF

Evans Thomas , 07-13-2026, 07:27 PM

JLC under 50x50 mm promo tier. You get 2 dollar 6 layer board with free ENIG and tented+capped vias in pad

QDrives , 07-13-2026, 09:33 PM

A 100nF capacitor on the output of the buck regulator is only used to filter out some higher frequency noise.
This in part comes from the parasitic capacitance of the inductor.
There is no need to treat that point as the best point to continue the power. In fact, it might be the worst.

I forgot to mention that you should not place traces below the inductor. Especially not the feedback!

Evans Thomas , 07-14-2026, 05:53 AM

Damn, I knew but missed that

Evans Thomas , 07-14-2026, 06:00 AM

moved the left FB trace to L5. Can I route the right one like this from the pad of the schottky?

QDrives , 07-14-2026, 01:36 PM

The 5V line for FB moves in 'parallel' with the windings of the inductor.
Even if the inductor is shielded, the shielding is the worse at the bottom.
Best to route the FB on another layer too.

Evans Thomas , 07-14-2026, 01:48 PM

Okay, thanks for all your help!

Evans Thomas , 07-14-2026, 01:49 PM

No problem for routing from the Schottky pad right?

Evans Thomas , 07-14-2026, 01:51 PM

And now I think of it, you said previously that the 0.1uF at the output would be the worst place to route the output from so I guess I want to change that fat trace anyway?

QDrives , 07-14-2026, 02:29 PM

"*No problem for routing from the Schottky pad right?*" - correct.
"*...would be the worst place...*" - **could be** the worst place. Do note that every trace has inductance. So in effect, you add another filter.

Evans Thomas , 07-14-2026, 02:35 PM

Then connected again on L5

Evans Thomas , 07-14-2026, 05:09 PM

Also, @QDrives, just thought about a grave problem. Normally for decoupling caps, the conventional advice I've seen is to route power into the caps first and then route the trace through the capacitor's pad and into the power pin. Here, I have a pour and several vias not before the capacitors. Does this mean I'm allowing noise or will the low inductance of the pour mean this is not a problem? And would I have anything to gain by dropping a via right on the input 0.1uF caps? Or for those alone, I should keep the vias before it?

QDrives , 07-14-2026, 07:43 PM

I think it is more important how you place the via **pair**. After all, it is not just the +5V (or whatever voltage), but also the Gnd return.
Placing the supply and return via side by side reduces the inductance.

Evans Thomas , 07-14-2026, 08:34 PM

Ah nice, yeah that certainly makes sense...