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BoloDia , 08-01-2026, 01:37 PM

Hey. Welcome everyone. I have one specific question. What if I have SIG-PWR/GND/GND/SIG-PWR stackup and I do not have any GND polygon pours on L1 and L4? Do I need to stich two internal GND planes together on their whole surfaces or maybe only in the places where my signals change the reference plane? Please provide justification.

, 08-01-2026, 01:43 PM

🤖 In the meantime, here’s a response from the [FEDEVEL AI HW Assistant]().
It helps to find relevant resources for your question, but it may make mistakes as it’s still in early development.

This is the response from the AI Assistant:
For your SIG-PWR/GND/GND/SIG-PWR stackup with no GND pours on L1/L4, here's the key insight:

**Critical stitching is required at signal reference plane transitions**, not across entire surfaces. Here's why:

1. **Adjacent GND planes (L2/L3)** naturally form a coupled pair through interplane capacitance, providing inherent high-frequency coupling between them. Full-surface stitching isn't mandatory if they're solid planes ([source](https://www.youtube.com/watch?v=ELe1RNa-WC4&t=721)).

2. **Signal transitions between layers** create return current discontinuities. When a signal moves from L1 (referencing PWR) to L4 (referencing PWR), its return current must transition between GND planes. This is where stitching vias near the signal vias become critical to:
- Provide low-impedance return path
- Prevent return current loops
- Reduce EMI ([source](https://www.youtube.com/watch?v=nPx2iqmVAHY&t=615))

3. **Key locations for stitching**:
- Near all signal vias crossing between L1/L4
- Around power plane splits/cutouts
- At board edges (every 1/10λ of highest frequency)
([source](https://www.youtube.com/watch?v=aAB6qMQwykg&t=1559))

4. **Exception case**: If your GND planes have splits/islands, you must stitch around the splits to maintain continuity. But for solid planes, localized stitching at transitions suffices ([source](https://www.youtube.com/watch?v=bU2Ef-2ZIK4&t=2088)).

Pro tip: Use 1 stitching via per 100-500mA of signal current (density increases with frequency). Always place them < 50 mils from signal vias for best results.

You can continue chatting with the AI Assistant here:
https://fedevel.com/hw-assistant

QDrives , 08-03-2026, 09:49 PM

You better add some stitching vias on the circumference. It help lower the cavity resonance that may occur.
https://www.youtube.com/watch?v=gHF5JyJF-N4

Robert Feranec , 08-07-2026, 11:52 AM

i do that at the places where signals are changing reference planes and only if there is no other via e.g. capcitor via