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Skoomadentist , 07-17-2026, 02:24 PM

I don't know why very few signal integrite books mention this or even outright act like such damping wouldn't be possible. It's all basic Circuit Theory 1 level stuff.

Skoomadentist , 07-17-2026, 02:26 PM

Ultimately what matters is the combination of 1) reducing noise at AVdd and particularly Vref and 2) keeping the impedance seen by AVdd low enough. Plotting the impedance like in that screenshot reveals both the impedance and any resonances that would outright increase noise at those frequencies.

Skoomadentist , 07-17-2026, 02:31 PM

Also that 4.7 uF cap is nowhere near as high as 4.7 uF if it's a 0402 capacitor because even 3.3V is enough DC bias to significantly reduce the capacitance.

Evans Thomas , 07-17-2026, 03:24 PM

What does R2 model again?

Evans Thomas , 07-17-2026, 03:34 PM

Is this correct? Removing the 0.1uF shows a single trough at about 2MHz before rising again. So I'm wondering if there's any value to having this ferrite anyway and if its better to just delete it... I have an AP2112K-3.3 providing the 3.3V

Skoomadentist , 07-17-2026, 03:51 PM

R2 is the series damping resistor required to damp resonance from L1 and C1 if R1 is low

Evans Thomas , 07-17-2026, 04:06 PM

Okay, thanks. Can you verify my plot?

Skoomadentist , 07-17-2026, 04:11 PM

Yes, you get a plot like that if you also simulate the series inductance of the capacitors

Skoomadentist , 07-17-2026, 04:16 PM

Are you simulating using a voltage source on left side or current source on the right? If the first, you're measuring only the noise attenuation but not the impedance seen by AVdd which can have a significant peak in the impedance.

Evans Thomas , 07-17-2026, 04:21 PM

Yes, I did a rough series inductance of 0402 package + vias and also ESR.

Evans Thomas , 07-17-2026, 04:21 PM

Did the current source on the right as you showed

Evans Thomas , 07-17-2026, 04:22 PM

So correct me - I'm thinking the ferrite is not worth having. This is for a Flight Cotnroller

Skoomadentist , 07-17-2026, 04:25 PM

What do you use AVdd for? Important ADC readings?

Evans Thomas , 07-17-2026, 04:40 PM

Um, not really. Just battery voltage and current readings from a shunt resistor

Evans Thomas , 07-17-2026, 04:41 PM

There could be a 50 Hz airspeed sensor too but for this I'm not really sure. Does that ferrite really improve the response? I'm a bit confused from the graph

Evans Thomas , 07-17-2026, 05:01 PM

Ahh okay, as you said, linear really helps.. I see there's value to using the ferrite. I tried the voltage source on the left and it seems this is good

Skoomadentist , 07-17-2026, 05:02 PM

It improves reliability / the chance of nothing above 100 kHz accidentally coupling into the ADC via the power network.

Evans Thomas , 07-17-2026, 05:03 PM

Thank you very much @Skoomadentist. I also saw that Eric Bogatin article on the multiple decoupling caps myth

Evans Thomas , 07-17-2026, 05:04 PM

So I can actually delete the 0.1uF caps... I learned something today

Evans Thomas , 07-17-2026, 06:03 PM

And just now as I was revising my design, I thought why not also change the 0.1uF caps on the buck regulators to something like a 0402 4.7uF. This must be better right?

Skoomadentist , 07-17-2026, 06:10 PM

Not necessarily at all! You need to consider what it does to the resonances and if they are stable with larger ceramics. You also need to account for the voltage coefficient.

Evans Thomas , 07-17-2026, 06:16 PM

I mean yeah the TI tested design is to have 2x 22uF (1206) and the design doesn't really say anythign about a max capacitance

Evans Thomas , 07-17-2026, 06:16 PM

Only min capacitance

Skoomadentist , 07-17-2026, 06:26 PM

Then you want 2x 22 uF in 1206

Evans Thomas , 07-17-2026, 06:28 PM

Yes already did that. they also show a 0.1uF in a smaller package st as I was saying, maybe replace that with a 4.7 or 10uF? Like to eke as much benefit as possible

, 07-17-2026, 06:33 PM

🤖 In the meantime, here’s a response from the [FEDEVEL AI HW Assistant]().
It helps to find relevant resources for your question, but it may make mistakes as it’s still in early development.

This is the response from the AI Assistant:
Your observations align well with best practices in analog power supply design. Let me break this down using insights from our video content:

1. **Ferrite Resonance Issues**:
Ferrite beads + capacitors create LC tanks that can ring. This is why damping networks (like your R68+C44) are critical. As shown in [this experiment](https://www.youtube.com/watch?v=HaLMjVkKYMw&t=2284), improper LC filtering without damping can create significant ringing noise. The solution matches your approach - adding resistance to lower Q factor.

2. **Capacitor Practice Evolution**:
The "0.1μF + 1μF" myth is indeed outdated with modern MLCCs. As explained in [our capacitor selection video](https://www.youtube.com/watch?v=bu4CWYFlOwg&t=762), today's small-form capacitors (0402/0201) achieve both high capacitance and low ESL. Separate 1μF caps for VDDA/VREF+ make sense unless they're <1mm apart.

3. **Ferrite Frequency Limitations**:
You're correct about ferrite effectiveness. As demonstrated in [this VNA measurement](https://www.youtube.com/watch?v=tkvmM9kk_GA&t=3273), ferrites only help above ~10MHz. Below 200kHz, their impedance is negligible - hence the need for your LDO for low-frequency rejection.

4. **Eval Board Caution**:
We've shown in [PCB layout reviews](https://www.youtube.com/watch?v=YzBtfN1LQtM&t=402) that many reference designs use ferrites incorrectly. Your approach of combining LDO (low-mid freq) + ferrite (high freq) + damping network matches what we recommend for sensitive analog supplies.

5. **Practical Implementation**:
Your RC damping network is smart.

, 07-17-2026, 06:33 PM

As seen in [this noise measurement](https://www.youtube.com/watch?v=hZSOhVdzqZk&t=2902), proper damping can eliminate resonance peaks. The 5-10× capacitor rule helps address the ferrite's DC resistance while maintaining low-Z at target frequencies.

Key takeaways from our content:
- Ferrites only work when paired with proper capacitance and damping
- Modern MLCCs make multi-value decoupling obsolete
- Separate analog supplies need individual attention
- Eval boards often prioritize simplicity over optimal PDN

Your implementation shows good understanding of these principles. The +-0.75 LSB noise result validates the approach.

You can continue chatting with the AI Assistant here:
https://fedevel.com/hw-assistant

QDrives , 07-17-2026, 09:51 PM

The NCP114 has about 30dB PSRR at 200kHz.
C19 and C20 should **not** be class II ceramic (X7R, X5R, Y5V, etc.)

QDrives , 07-17-2026, 09:53 PM

If you want to save cost, replace the ferrite / inductor with a resistor. Something like 1 Ω.

QDrives , 07-17-2026, 09:58 PM

The resistance to use is SQRT(L/C)

Skoomadentist , 07-17-2026, 10:03 PM

I have the ferrite there to filter > 1 Mhz spikes away (yes, it does have a measurable effect in the circuit). And the capacitors are X7R explicitly and on purpose.
But this is a separate discussion and not relevant to this thread.

QDrives , 07-17-2026, 10:17 PM

You mentioned the LDO for the low to mid frequency. 200kHz is a typical SMPS frequency and just at that point the PSRR fails most LDOs. passive filter often just start at about that frequency.

Evans Thomas , 07-18-2026, 05:18 AM

I am using an AP2112K LDO with -65dB to directly supply the digital part from which I'm filrering for analog

QDrives , 07-18-2026, 04:10 PM

The AP2112 has about -35dB @ 200kHz. Graph stops at 100kHz so I had the extrapolate.
And your filter has about -12dB at 200 kHz (taking the LTSpice plot).
So about 47dB in total. If you have 10mV ripple on the input of your LDO, that gives you 45uV on analog.

However, noise on you 3.3V due to the MCU (and others) is only filtered with the -12dB filter.
What do load steps on the 3.3V do?

Evans Thomas , 07-18-2026, 05:53 PM

I'm not sure where that number comes from.

Evans Thomas , 07-18-2026, 05:54 PM

Evans Thomas , 07-18-2026, 05:55 PM

Oh really sorry, you said 200Khz. I read it as 2khz

Evans Thomas , 07-18-2026, 05:55 PM

What does "load step" mean?

Evans Thomas , 07-18-2026, 06:05 PM

Also the STM32H5 uses 12 bit ADC with an ENOB of maybe 9 or 10 bits. So I guess noise upto a mV is negligible anyway although I havent estimted the input noise from the buck

QDrives , 07-18-2026, 07:56 PM

Lets say you have a load step of 10mA (MCU does heavy calculation after a rest period, peripheral use, IO switching, etc.)
Your regulator corrects that in 1us (which is very fast). AP2113 does not provide much data on this.
You have 10uF load capacitance.
Q = C * dV -> 10m * 1u = 10u * dV -> dV = 1mV

QDrives , 07-18-2026, 08:00 PM

ENOB is 10.8 bits taken this datasheet https://www.st.com/resource/en/datasheet/stm32h5e5ij.pdf

Evans Thomas , 07-19-2026, 03:48 AM

Okay

Skoomadentist , 07-19-2026, 12:06 PM

FWIW that 10.8 isn’t just theoretical. I have a prototype using STM32F411 (same enob spec for adc) that gets more or less exactly that before any oversampling or digital filtering. You’ve already seen the analog supply and the adc input is buffered by a nearby opamp to keep source impedance low during the sampling.

Evans Thomas , 07-19-2026, 12:23 PM

Great, good to know

Skoomadentist , 07-20-2026, 01:18 PM

BTW, this doesn't appear to be correct according to https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/196/Optimal_5F00_single_5F00_resistors_5F00_damping_5F00_of_5F00_input_5F00_filters.pdf (see section V, pdf page 4)

QDrives , 07-20-2026, 06:35 PM

That has to do with the shift of the frequency. But the initial R0 is shown as I mentioned.

BoloDia , 08-01-2026, 02:30 PM

How did you measure the noise?

BoloDia , 08-01-2026, 02:32 PM

Could you link that video, please?

Skoomadentist , 08-01-2026, 04:08 PM

I printed a whole bunch of values from each ADC channel to uart and noticed that they were always some number +-1. That comes out to roughly +-0.75 LSB in log scale. It's a ballpark anyway, not an exact measure.

Skoomadentist , 08-01-2026, 05:38 PM

It was actually an Altium Academy video:
https://www.youtube.com/watch?v=fdkb1O_Om7Q