FEDEVEL
Platform forum

Kristóf Kanics , 02-29-2024, 01:10 PM

Their support told me 0.254mm which sounds a bit restrictive... From their website it is not quite clear for me.

Mini , 02-29-2024, 03:56 PM

If their support told you this then that's their capability and we can't change that. I don't know why not do a quick google search if you are hesitating(literally first answer in google search): https://easyeda.com/forum/topic/Via-to-Pad-clearance-834a12ba1d0341ff83a20f39bdad8c8f

Mini , 02-29-2024, 03:57 PM

According to this via to pad is same as via to track and via to track you can see on their homepage under capabilities.

Mini , 02-29-2024, 03:58 PM

QDrives , 02-29-2024, 05:19 PM

What a set of terrible pictures (dimension lines).
But you are right, the clearance between via and track (copper <-> copper) is the same as track to track.
However, I would need to add one possible exception and that is breakout - so if you are going for the smallest of everything (TT, TW, OAR/IAR and via hole size), you might get some problems (for thin copper <= 35um)
In my opinion Eurocircuits show it more clearly https://www.eurocircuits.com/pcb-design-guidelines/classification/

Kristóf Kanics , 03-01-2024, 09:15 AM

@QDrives Thank you for your reply. Eurocircuits' guide is really much more intuitive. For JLC, track-to-track is described a little bit further below, 0.09mm for 4-6 layers, 0.127mm for 1-2 layers.

Anyway, I found my problem... I typed 0.254mm for via-pad clearance. JLC measures it from hole to pad, but Altium measures it from outer ring to pad. Same confusion in the google search result @Mini linked. That's why it seemed to be very restrictive. I couldn't fan out a 0.8mm BGA with those rules.

Mini , 03-01-2024, 10:40 AM

JLCPCB indeed isn't very good at defining clearances.

QDrives , 03-01-2024, 02:45 PM

That is why I said "What a set of terrible pictures (dimension lines)."
I see that the Eurocircuits picture is missing copper thickness. That limits the classes possible.