antman , 03-25-2019, 11:15 AM
Hi Robert and everybody,
I am currently working over a layout of a board which integrates a DDR4-64 bits bank, and I have some doubts about length matching (this question can be extended to any differential pair). I have attached a image where you can see a example of differential signal, concretely the clock signal of DDR4. The match length of the Command - Address - Control signals is performed, but intra-differential pair needs to be corrected yet, with a difference between P and N of aprox. 1mm, and a goal tolerance of 0.1mm.
I have read a lot about length matching solutions in differential pairs, but I am not sure what can be the best solution to my problem.
The main question is where to place the matching length. There are three possible places: at the start (FPGA), along the track or at the end (1st memory). At the extremes, the advantage is that the impedance is constant during most of the travel, but the differential phase will increase, and therefore, the jitter and the common mode noise. If we match the signal along the track, where mismatch appears, we will insert points where the differential impedance change the value, and I think this also affects to signal integrity. What is your advice?
Regarding to the matching method, what do you think is better? Smooth Sawtooth or Strong Trombone?
Thank you very much!