LVPECL clock buffer output termination
mairomaster , 02-12-2016, 02:36 AM
Hi guys,
I am working on a reasonably complex board with many different components - CPUs, FPGAs, a bunch of interfaces, etc. I have a few copies of the board manufactured and I have been testing them in the past 2 weeks. All modules/interfaces seem to work fine so far but there is a problem.
I am using a 10G PHY connected to an FPGA for 10G networking. The PHY didn't seem to work at all and eventually I found that the problem is the common mode voltage level of the reference clock supplied to it.
Here is a description of my system:
The reference clock of the PHY is 156.25 MHz and is supplied by a LVPECL differential clock buffer.
For the clock buffer I use Silicon Labs 53306 with 2.5V supply voltage:
The buffer is configured to work in LVPECL output mode, as the input of the PHY requires. In such mode the common mode voltage at the output should be 0.9 - 1.25 V (page 5 of the datasheet).
One of the outputs of the buffer is directly connected to the input of the PHY, without any termination. The PHY is supplied by multiple filtered power nets, each of them running at 1.2 V. In the PHY the two signals in the clock differential pair are internally terminated with 2 50ohm resistors to a termination voltage of 0.8 V, generated by a voltage divider (see attached image). The common mode voltage at the input of the PHY by specifications is supposed to be between 0.7 V and 0.95 V.
With the described configuration the PHY would not work. The common mode voltage at the input was measured to be about 2.1 V (across all boards), which supposedly saturates the clock input stage. I tried to AC couple the input and add 2 90ohm DC coupling resistors to ground at the outputs of the buffer (datasheet page 15) and the PHY started working right away. In this case the common mode voltage at the input of the PHY is 0.8V (properly set by the bias circuit) and the common mode at the output of the buffer is 1.2 V.
I have a couple of questions regarding the initial problem:
1. Why are the buffer and PHY specified to use LVPECL differential signalling and at the same time specify common mode voltages which are much below 2 V. As far as I know, the LVPECL standard uses a common mode voltage of 2V.
2. Direct DC coupling is one of the allowed termination schemes for the buffer (Scheme 2, page 15). Why am I getting 2.1 V common mode voltage at the output of the buffer if by specifications it should be 0.9 - 1.25 V? Isn't the 0.8V bias voltage in the PHY supposed to correct that?
Thanks.
I am working on a reasonably complex board with many different components - CPUs, FPGAs, a bunch of interfaces, etc. I have a few copies of the board manufactured and I have been testing them in the past 2 weeks. All modules/interfaces seem to work fine so far but there is a problem.
I am using a 10G PHY connected to an FPGA for 10G networking. The PHY didn't seem to work at all and eventually I found that the problem is the common mode voltage level of the reference clock supplied to it.
Here is a description of my system:
The reference clock of the PHY is 156.25 MHz and is supplied by a LVPECL differential clock buffer.
For the clock buffer I use Silicon Labs 53306 with 2.5V supply voltage:
The buffer is configured to work in LVPECL output mode, as the input of the PHY requires. In such mode the common mode voltage at the output should be 0.9 - 1.25 V (page 5 of the datasheet).
One of the outputs of the buffer is directly connected to the input of the PHY, without any termination. The PHY is supplied by multiple filtered power nets, each of them running at 1.2 V. In the PHY the two signals in the clock differential pair are internally terminated with 2 50ohm resistors to a termination voltage of 0.8 V, generated by a voltage divider (see attached image). The common mode voltage at the input of the PHY by specifications is supposed to be between 0.7 V and 0.95 V.
With the described configuration the PHY would not work. The common mode voltage at the input was measured to be about 2.1 V (across all boards), which supposedly saturates the clock input stage. I tried to AC couple the input and add 2 90ohm DC coupling resistors to ground at the outputs of the buffer (datasheet page 15) and the PHY started working right away. In this case the common mode voltage at the input of the PHY is 0.8V (properly set by the bias circuit) and the common mode at the output of the buffer is 1.2 V.
I have a couple of questions regarding the initial problem:
1. Why are the buffer and PHY specified to use LVPECL differential signalling and at the same time specify common mode voltages which are much below 2 V. As far as I know, the LVPECL standard uses a common mode voltage of 2V.
2. Direct DC coupling is one of the allowed termination schemes for the buffer (Scheme 2, page 15). Why am I getting 2.1 V common mode voltage at the output of the buffer if by specifications it should be 0.9 - 1.25 V? Isn't the 0.8V bias voltage in the PHY supposed to correct that?
Thanks.
robertferanec , 02-13-2016, 03:51 AM
Wow, that was a quite hard problem to solve. Well done @mairomaster
I am always very careful about clock buffers - there is number of different specifications. Normally I try to follow recommendations from reference designs. I have seen situations when datasheet specified something, but reference schematic was using something different - and it worked oki. They never explain why they changed it
. If I am not sure, or if I use a new chip, I add different termination options directly into schematic and during testing adjust it.
I am always very careful about clock buffers - there is number of different specifications. Normally I try to follow recommendations from reference designs. I have seen situations when datasheet specified something, but reference schematic was using something different - and it worked oki. They never explain why they changed it
. If I am not sure, or if I use a new chip, I add different termination options directly into schematic and during testing adjust it.Use our interactive Discord forum to reply or ask new questions.