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Decoupling Cap Fanout Under BGA
dansteinb , 08-16-2016, 01:13 PM
I'm really struggling with the decoupling cap fanout under the BGA. Can you provide more examples of how to do this properly? I especially get into trouble when I have a larger cap to place
nachodizz990 , 08-16-2016, 02:00 PM
Place a Pic of your layout, what is the cap size?
- Make your final board tickness the ticker the better, and the cap vÃas the wider the better also try to place the bigger capacitance that your cap size allows.
- Then place the cap and the cap vias close to the bga pad you want to decouple.
- Make the distance and trace width from the cap pads to the vÃa the smallest and wider you can
- If you have a BGA gnd vÃa very near to the place you fit the capacitor then route the cap gnd to that via
- If you dont have a gnd via near the capacitor then make a square gnd plane under your bga on the bottom side and connect directly the capacitor to that plane.
- Then stitch the bottom plane with vias as close as you can to the place you placed the capacitor
- Try to imagine what can be the shortest current loop you can design and how the current will flow
About good examples you can download the OpenRex and I.Mx Rex boards, in adittion you can download all the Texas Instruments Boards designs from the TI´s page and watch the layout with Allegro Free Physical Viewer.
The more professional designs you look at, the more welldone tips you will learn
PD: Dont share a cap gnd pad and a IC gnd pad if you´re on the same layer, if you´re on opposite layer you can go with that, if you´re on the same layer you ´re placing the noise decoupled by the capacitors directly to the IC gnd pin
If you have to do it on the same layer, then place the via between the cap and the ic pin
Also rememver that always you place a via to connect a cap pad you´re placing series resistance and inductance to the cap, but everybody knows that this fact is unavoidable
- Make your final board tickness the ticker the better, and the cap vÃas the wider the better also try to place the bigger capacitance that your cap size allows.
- Then place the cap and the cap vias close to the bga pad you want to decouple.
- Make the distance and trace width from the cap pads to the vÃa the smallest and wider you can
- If you have a BGA gnd vÃa very near to the place you fit the capacitor then route the cap gnd to that via
- If you dont have a gnd via near the capacitor then make a square gnd plane under your bga on the bottom side and connect directly the capacitor to that plane.
- Then stitch the bottom plane with vias as close as you can to the place you placed the capacitor
- Try to imagine what can be the shortest current loop you can design and how the current will flow
About good examples you can download the OpenRex and I.Mx Rex boards, in adittion you can download all the Texas Instruments Boards designs from the TI´s page and watch the layout with Allegro Free Physical Viewer.
The more professional designs you look at, the more welldone tips you will learn
PD: Dont share a cap gnd pad and a IC gnd pad if you´re on the same layer, if you´re on opposite layer you can go with that, if you´re on the same layer you ´re placing the noise decoupled by the capacitors directly to the IC gnd pin
If you have to do it on the same layer, then place the via between the cap and the ic pin
Also rememver that always you place a via to connect a cap pad you´re placing series resistance and inductance to the cap, but everybody knows that this fact is unavoidable
robertferanec , 08-17-2016, 06:44 PM
The big caps do not have to be directly under BGA, unless they are part of smaller power rail. Think about the placement and start from the middle of the BGA. Also, you really may want to place all the through hole VIAs when you will be doing decoupling placement, so you are sure you can fanout all the signals. As @nachodizz990 mentioned, maybe have a look at some of our designs - you can download full altium project files of OpenRex and also iMX6 Rex module. You may find it useful.
nachodizz990 , 08-18-2016, 12:23 AM
- I forgot it!
As @robertferanec said, the biger caps are intended to filter low frecuencies, medium caps medium frecuencies and small caps high frecuencies, this last caps (smaller caps for filtering HF) should be closer to the pin.
- Sometimes you will see that some reference designs include a lot of small equal capacitances, they can be intended for create a large capacitance with very low inductance and ESR or for serve as individual pin decoupling, you most observe if the number of small caps equals the pin count, if yes probably they are intended to place near the pin, and the medium caps more away from the pin to act as bulk capacitance for the local plane area.
-If not, the best way it´s to act by "common-sense" analyce the network and try to find a logical approach.
- Agood example about all of this, it´s the OpenRex Ethernet Phy decoupling and placement scheme, try to observe the schematic, and the component placement, look how they placed small capacitances near the pins and medium caps to filter the local plane that provides power to the small caps.
Its imposible to imagine how electrons and holes will flow but acting by common sense all will be more or less right
I´m altera lover but this is one of the most complete guidelines i ever seen
As @robertferanec said, the biger caps are intended to filter low frecuencies, medium caps medium frecuencies and small caps high frecuencies, this last caps (smaller caps for filtering HF) should be closer to the pin.
- Sometimes you will see that some reference designs include a lot of small equal capacitances, they can be intended for create a large capacitance with very low inductance and ESR or for serve as individual pin decoupling, you most observe if the number of small caps equals the pin count, if yes probably they are intended to place near the pin, and the medium caps more away from the pin to act as bulk capacitance for the local plane area.
-If not, the best way it´s to act by "common-sense" analyce the network and try to find a logical approach.
- Agood example about all of this, it´s the OpenRex Ethernet Phy decoupling and placement scheme, try to observe the schematic, and the component placement, look how they placed small capacitances near the pins and medium caps to filter the local plane that provides power to the small caps.
Its imposible to imagine how electrons and holes will flow but acting by common sense all will be more or less right
I´m altera lover but this is one of the most complete guidelines i ever seen
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