DDR II SDRAM PIN ASSIGNMENTS
mohsin_qau , 11-09-2017, 06:47 AM
I have designed custom PCB in which i have interfaced Cyclone III FPGA with DDR II SDRAM. I have used all the designing techniques that i have learnt from Robert.In the designing phase, i assigned the pins with FPGA and synthesize the project. The fitting report was successful. I have designed the Board with this pin assignments.
When i bring up the board and perform DDR II Memory controller timing constraints and synthesize the project, it gives the error that DDRII_UDM pin is failed to be assigned in wrong location. I am stuck at that point.
I have studied the Altera Cyclone III app notes. In the forum , one of the pupil has said that if u didnot perform masking on write byte, you have to ground them.
Is this scheme can work for me?Why this error at this stage? If it was wrongly assigned then why its come occur in initial stage?
When i bring up the board and perform DDR II Memory controller timing constraints and synthesize the project, it gives the error that DDRII_UDM pin is failed to be assigned in wrong location. I am stuck at that point.
I have studied the Altera Cyclone III app notes. In the forum , one of the pupil has said that if u didnot perform masking on write byte, you have to ground them.
Is this scheme can work for me?Why this error at this stage? If it was wrongly assigned then why its come occur in initial stage?
robertferanec , 11-10-2017, 05:04 PM
Hmm, only what I can think about from schematic/layout point of view is if the mask pins are correctly grouped with associated data bytes ... I am not sure about implementation in FPGA code.
mohsin_qau , 11-13-2017, 02:06 AM
Data Mask Pins are associated with Respective data bytes. But the fitter report gives failure. Schematics is attached.
robertferanec , 11-13-2017, 06:44 PM
How are you connecting them to the memory chip and how did you create the BANK groups (e.g. BANK0: DDR1D0-7, DDR1_LDM, DDR1_LDQS)? UDM is upper byte (8-15), LDM is lower byte (0-7). From the screenshot which you attached it looks to me, that you may have UDM and LDM swapped - but I would need to see the chip connection.
mohsin_qau , 11-13-2017, 09:18 PM
Sir, Please find the DDRII Pins.
mohsin_qau , 11-13-2017, 09:57 PM
I have assigned FPGA Bank 7 for DDRII_D0-D7, DDRII_LDQS, DDRII_UDQS, DDRII_UDM & DDRII_LDM..........& Bank 8 for DDRII_A0-A12, CAS, RAS,WE,CS,CKE,CK_P,CK_N,ODT & Bank Addresses.
mohsin_qau , 11-13-2017, 11:17 PM
Sir, with your effort, problem is resolved with pin swapping of UDM & LDM.
robertferanec , 11-14-2017, 06:48 AM
So, when you swapped UDM & LDM, it now works? 
mohsin_qau , 11-14-2017, 11:02 PM
Yes sir. with pin swapping......fitter error is removed. Now i run Memory test through NIOS processor. We are using Altera CycloneIII 484 BGA FPGA. But the test fails at the inital address. Can u have any experiencing with that?
robertferanec , 11-15-2017, 08:52 AM
How did you swap the pins, in your FPGA code or on the board? Also, how the length matching is done (when you swapped the UDM & LDM, is the data bank length matching correct)?
mohsin_qau , 11-17-2017, 02:29 AM
In the FPGA Code.Yes sir, Data bus, Data Strobe & Mask pins lengths are matched.
robertferanec , 11-17-2017, 06:48 PM
Did you match all the data signals (data, strobe, mask) to the same length? Or you length match them based on banks?
I am asking as I am trying to understand if the signals are correctly split into databanks.
I am asking as I am trying to understand if the signals are correctly split into databanks.
mohsin_qau , 11-22-2017, 01:40 AM
I perform Length matching based on differential clock.
robertferanec , 11-22-2017, 05:03 PM
I am not sure what you mean by "I perform Length matching based on differential clock."
Do you do something like this: https://www.fedevel.com/welldoneblog...atching-rules/
The picture is for DDR3, but it is similar for DDR2. Check out especially the DATA BYTES (yellow and green block) - you need to have your databanks length matched correctly. And because your UDM and LDM signals were swapped, I am just pointing out, that they may be length matched according to different data group.
Do you do something like this: https://www.fedevel.com/welldoneblog...atching-rules/
The picture is for DDR3, but it is similar for DDR2. Check out especially the DATA BYTES (yellow and green block) - you need to have your databanks length matched correctly. And because your UDM and LDM signals were swapped, I am just pointing out, that they may be length matched according to different data group.
mohsin_qau , 12-04-2017, 10:16 PM
Yes Sir. I got ur point now. Yes i have matched the length according to the given diagram.
robertferanec , 12-05-2017, 12:58 PM
Then I am not really sure what the problem can be 
Maybe you have already sorted it out
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