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muse , 03-26-2018, 10:26 AM

Hi all,
i'm new to Altium, i'm trying to learn by myself and with the help of fedevel courses..
I used Cadence for almost 6 years then my company switched to altium and gave me time and budget to learn and build my first High Speed Design.
Usually we worked with Cortex M4 MCU from STM, so HSD was not our priority... but now we begin to use M7 and try to realize more integrated boards, with
external memory and exposed bus (32bit).
I'm trying to follow Robert's recommendations i learned on its course, and using schematics form ST demo boards as reference design..
I've never done a tuned bus, so i started placing MCU and other components involved in the 32bit bus: a SRAM and a connector for another board.
I used T-branch topology, and my first impression is that i'm extremely slow.... As you can see i have the MCU on the top, memory on the left side and connectors on the right ..
At this point i have a doubt: should i try to restrict the tracks of the bus or should i start to tune them ?
I feel like every step i can take now it's wrong..

Any suggestion would be appreciated
Thank you in advance for your help.
Bye

robertferanec , 04-02-2018, 10:16 AM

I am not exactly sure about CPU and memory which you are using, but I would probably consider to use buffers. On the layout in your picture you may get a lot of reflections from the cable side and it may completely damage the signals - so for example you may have troubles to access the memory.

muse , 04-05-2018, 09:06 AM

Hi Robert,
Thank you for your reply.
I know that T-branch could be not the right topology, but the board i'm trying to design it's a demo board where i should mount another board on the bus interface.

I'm using this board to practice with High Speed design and i wanna follow all possible rules to design it properly.
I'm using a STM32F7 uC with a 32bit bus to connect a Sdram, a Nand Flash and a transceiver chip.
In this first stage, the transceiver chip will be connected through its demo board (attached picture, AXM88180-EVB-RTL8211E-1 SMDK2440 , from Asix), but in the final design it will be placed directly on the my PCB, my company has the End User Agreement to use it.

I'm little confused about the topology i should use.
I have a demo board of the STM32F7 (attached picture, cadence pcb) , where the bus is connected in a similar way, first with two connectors and then to memory chips (nand and sdram).
is it better to use a fly-by topology i suppose in order to avoid reflections ?
Maybe i can route hte bus in some way first to the connectors i have to use for the demo board plug, and then to the memory chips trying to tune them (fly-by) ?? ...
I just wanna solve this before proceed with consideration about timings. Some people in other forums told me that probably some reflections will occours, but even without using High Speed Design rules it should work.. I'm not shure about this, anymay i have to practice with High Speed Design and i want to to things in the right way.. at least i want to try...

Thank you.

robertferanec , 04-05-2018, 10:51 AM

That is a very interesting layout. I see it is 90MHz interface, but still connecting 3 chips + connector, wow. I am surprised that the bus is working ok.

I would not speak here about T-branch of Fly-by. They placed the connector on the way to the memories to minimize reflections from the stubs which are caused by the unconnected connector. In your case, if connector is not connected, the stub is much bigger and can cause bigger reflections, possibly it could also work as an antenna (that is bad).

Maybe they simulated it (used the memory models and tried to simulate different scenarios - read and write from different chips) and they found out, that it will work ok for that frequency.

If you only have one flash, memory and one connector, you could place the connector on the way to the flash. However, do not forget, a lot will depend on how the thing to the connector is going to be connected (e.g. if you will be using cable or if it is board to board ... what kind of chip is there and what speed you will be using). Using buffers is always safe (it could isolate your MCU-FLASH bus from the CONNECTOR - UNKNOWN CIRCUIT)

muse , 04-13-2018, 02:11 AM

Good morning Robert, thank you for the reply,
i'm finishing other parts of pcb before i can focus on the bus, trying to gain some skill with altium (i come from 6 years of pcb design with Cadence, i'm new to altium).
About the connector, i'll be using it for a board-to-board connection , in order to plug the gigabit controller demo board (the pic attached to previous post) on top of my board.
I'm considering your suggestion about the use of buffers, i had a look to voipac documentation of , i saw a board that has a similar configuration to mine (mcu, flash, sdram, connector) , the PXA255 dimm module, but they don't give schematics or pcb files , so i'm looking for some Application Note about the use of buffer in memory bus.
Thank you.

robertferanec , 04-16-2018, 10:34 AM

You can find some info about the PXA255 baseboard here:

muse , 05-07-2018, 01:40 AM

GoodMorning Robert,
if i use buffers, how should i place them in the bus respect to other components ?
I took a look to some designs with both memories and connectors on the bus.
For Example this SOM that i used several times, LPC4357 OEM BOARD from Embedded Artists:

They put connector and Nand Flash after the buffer,




Even if we found some errors in their schematic, the bus communication worked always without problem.

In my case i wanna place buffers just before connector, but now that i saw the LPC4357 layout i'm not so sure...
What do you think about it ?

Thank you.

robertferanec , 05-08-2018, 09:07 AM

I would also probably placed the buffers before the connector.

muse , 06-05-2018, 06:44 AM

Good morning,
i keep thinking to my design, among my different commitments..
After i convinced my self to put buffers to isolate sdram and flash from connector, i'm goingo to think to the layout and the placement of the components... thinking ahead to the lenght-matching needs.
First of all i think to place buffers as first element on the bus, then continue to memory chips with lengh-matching, like i tried to describe in the image .


Any suggestion would be appreciated
Thank you,
Bye.

robertferanec , 06-11-2018, 11:29 AM

Yes, your picture above is probably the way how I would try to do it. I would then try to simulate the layout, just to be sure there are no excessive reflections and signal quality is ok.