How to solve timing margin issues from fabrication side in custom hardware design ?
Kulunu , 04-06-2018, 08:57 AM
Hi All,
This is regarding i.MAX6Q based custom hardware design and I'm having timing margin issues in I/O interface between chipset and dram. If I/O interface margin is poor by routing issue or layout, it may cause failure depending on noise pattern ( different application make different noise level). So to solve this issue what do you suggest ?
1) Can we do this using chipset design option to control this kind of timing like phase shift for tDQS and tDQ.? Can you explain how to do this ?
2) Is it possible to down operating frequency ( ex 2400Mbps --> 2133Mbps ) How can we do this in uboot level (uboot boundary devices 2016)?
3) If it is related to clock timing, We can add capacitance or change termination resistance on CLK and CLK/. To do this what we should do ? Which parameter should I change in DDR initialization script before do memory calibration ?
Regards,
Kulunu.
This is regarding i.MAX6Q based custom hardware design and I'm having timing margin issues in I/O interface between chipset and dram. If I/O interface margin is poor by routing issue or layout, it may cause failure depending on noise pattern ( different application make different noise level). So to solve this issue what do you suggest ?
1) Can we do this using chipset design option to control this kind of timing like phase shift for tDQS and tDQ.? Can you explain how to do this ?
2) Is it possible to down operating frequency ( ex 2400Mbps --> 2133Mbps ) How can we do this in uboot level (uboot boundary devices 2016)?
3) If it is related to clock timing, We can add capacitance or change termination resistance on CLK and CLK/. To do this what we should do ? Which parameter should I change in DDR initialization script before do memory calibration ?
Regards,
Kulunu.
robertferanec , 04-08-2018, 05:35 PM
Have you run calibration? What were the results?
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