Dependency of tCL and tCWL values on custom hardware performance ?
Kulunu , 09-03-2018, 11:37 PM
Hi All,
My custom hardware is based on i.MX6Q processor and 800MHz Alliance DDR3 memory AS4C256M16D3A-12BCN.Design is most related to open rex ddr layout design.
I set tCL = 6 and tCWL = 8 for the calibration and ddr init script. Some boards are working for this values and for some boards I had to change tCWL = 7 for better performance. Otherwise getting segmentation faults.
1) How this could happen with the same ddr layout and same production line boards ? What can we figure with this fine tuning of tCL and tCWL value of board to board ?
A well as I could see following write DQS delays for my boards. You can see DQS 3 and DQS 4 are way off. It should be lover than 1/8 according to NXP user manual.
2) What can we say from following DQS results ? Is it a impedance problem of those byte lanes ?
3) To optimize above values I used following method. But I couldn't see any impact for DQS 3 and DQS 4 with WALAT changes. Why is that ?
4) What are the other dependency which we can tolerate like tCWL and tCL for the memory performance ?
Here I have attached DDR3 memory data sheet and NXP calibration tool results.
I must be thankful to you if you will kindly reply me soon.
Regards,
Kulunu.
My custom hardware is based on i.MX6Q processor and 800MHz Alliance DDR3 memory AS4C256M16D3A-12BCN.Design is most related to open rex ddr layout design.
I set tCL = 6 and tCWL = 8 for the calibration and ddr init script. Some boards are working for this values and for some boards I had to change tCWL = 7 for better performance. Otherwise getting segmentation faults.
1) How this could happen with the same ddr layout and same production line boards ? What can we figure with this fine tuning of tCL and tCWL value of board to board ?
A well as I could see following write DQS delays for my boards. You can see DQS 3 and DQS 4 are way off. It should be lover than 1/8 according to NXP user manual.
2) What can we say from following DQS results ? Is it a impedance problem of those byte lanes ?
3) To optimize above values I used following method. But I couldn't see any impact for DQS 3 and DQS 4 with WALAT changes. Why is that ?
4) What are the other dependency which we can tolerate like tCWL and tCL for the memory performance ?
Here I have attached DDR3 memory data sheet and NXP calibration tool results.
I must be thankful to you if you will kindly reply me soon.
Regards,
Kulunu.
robertferanec , 09-04-2018, 03:40 AM
This is the reason why I often use similar memory chips as are used on the reference design. I have tried to play with memory controller values in past and my settings never worked as good as the settings from reference boards.
Maybe try to find a board which is using same memories as you do and have a look into their source code - have a look how they setup the memory controller.
Possibly try your board with different memory chip e.g. Micron (where you know the memory controller settings) - just to be sure layout is perfectly fine - and then use different memory chips.
To setup memory controller may be sometimes tricky. Do not forget to test you memory settings in environmental chamber - many times memories can run just fine on your table in your office, but can be failing (and they should not be failing) in freezing temperatures. So, even some of your boards appear to be running fine, maybe they are just running on the edge (e.g. they may be failing in environmental chamber). Once the controller is set correctly, you should get consistent results - all the boards should work ok.
Definitelly run stressapptest (that will help you to see if your memory settings are really reliable):
http://www.imx6rex.com/software/stre...#stressapptest
This may also help: http://www.imx6rex.com/open-rex/soft...ental-chamber/
Maybe try to find a board which is using same memories as you do and have a look into their source code - have a look how they setup the memory controller.
Possibly try your board with different memory chip e.g. Micron (where you know the memory controller settings) - just to be sure layout is perfectly fine - and then use different memory chips.
To setup memory controller may be sometimes tricky. Do not forget to test you memory settings in environmental chamber - many times memories can run just fine on your table in your office, but can be failing (and they should not be failing) in freezing temperatures. So, even some of your boards appear to be running fine, maybe they are just running on the edge (e.g. they may be failing in environmental chamber). Once the controller is set correctly, you should get consistent results - all the boards should work ok.
Definitelly run stressapptest (that will help you to see if your memory settings are really reliable):
http://www.imx6rex.com/software/stre...#stressapptest
This may also help: http://www.imx6rex.com/open-rex/soft...ental-chamber/
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