FEDEVEL
Platform forum

sam , 07-29-2025, 02:12 AM

Hello, I am using keysight PDN analyzer from Altium tool as they provide a free trial. I am seeing a failure on +1V rail which is used for my DDR3 power supply on FPGA. Error says that current density is too high when current is going out of chip. I configured current to be 1.25A in the simulation. Is this necking down a real issue or is it okay as long as it's being connected to lower current density area in the power plane?

Other question is, voltage rail for DDR3 (+1V) is within +/-5%. I am seeing a voltage drop of 300mV (3%) when it arrives to FPGA pinouts. What should I do to minimize the drop? I did replace inductor that has lower DCR (13.5mohm max) but is there anything else that I can do about this? I thought 3% is too close to the requirement.

Thank you

sam , 07-29-2025, 02:13 AM

Above planes are part of below schematic (buck converetr output -> inductor output -> FPGA power pins)

QDrives , 07-29-2025, 02:16 AM

This picture is unreadable.

sam , 07-29-2025, 02:21 AM

Simulation configuration (Maybe my simulation profile is wrong.. )

sam , 07-29-2025, 02:24 AM

@QDrives Do you still have problem to seeing it? Let me know. Thanks

QDrives , 07-29-2025, 02:29 AM

Can you widen the trace closer to the IC? Even if it is double the current width.

Robert Feranec , 07-31-2025, 11:18 AM

the chip will be monitoring the output voltage, so only the drop between feedback and cpu power pins is important (that looks much less then 300mV .. maybe 30mV ?). also, I believe the connection from the pin to inductor will be fine - just try to make the connection wider (e.g. immediately as you go out of the pin make it wider). If the current is only 1.25A that is not a big current.