FEDEVEL
Platform forum

HasanTheSyrian_ , 11-11-2025, 01:18 PM

https://www.altium.com/viewer/?token=%2BWfb27nTjk609L4fgLyKE7%2Fq

https://imgur.com/a/CPrJwV1

**Notes:**

HDMIs use different banks as Vivado internal noise calculations (SSN) report high noise margins when the entire bank is used at once, especially at higher drive strengths, which might be needed because of the somewhat long trace length. AC termination used (resistors unplaced/DNP) since series termination can't be placed on the SOM. HDMI 2 (left) data, clk, and syncs length matched to +-10mm.

Ethernet length matched 2mm between pairs, 1mm within pairs. PHY on SOM; using FPGA hardcore.

MIPI length matched 1mm between pairs, 2mm within pairs. Implemented XAPP894 MIPI D-PHY (passively via the resistors you see).

JTAG/UART can be used via USB (at the same time) or via headers. Right USB connector can be toggled to be used as normal USB or for prog/debug.

USB PHY on SOM, USB Hub on dev board

There are no power planes, power is routed. All planes are ground. SIG/GND/SIG/GND/GND/SIG

Used return vias whenever possible to minimize reflections within the dielectric.

**Possible concerns:**

Power inductor choice: XGL4020-222MEC

HDMI_1V8 and FTDI_1V8 switching on at the same time

Length matching within MIPI pairs seem too much for the amount that they are misaligned.

Floating copper (star and constellation) acting as antennae

Sniper2 , 11-11-2025, 05:00 PM

did u also post on reddit?

Sniper2 , 11-11-2025, 05:00 PM

seems super familiar

HasanTheSyrian_ , 11-11-2025, 05:08 PM

yh

QDrives , 11-11-2025, 09:16 PM

Make sure you have the reset circuit correct with FTDI.
I have some bad experience with FTDI (as a user, not designer).

QDrives , 11-11-2025, 09:22 PM

Is Vbus1 (perhaps also others) a power input or power output?

QDrives , 11-11-2025, 09:24 PM

Both HDMI_1V8 and FTDI_1V8 are from linear regulators. Both get their power from VDD_3V3.
So what is your question about 'switching'?

QDrives , 11-11-2025, 09:28 PM

You could place a big copper area for the star and constellation. 'Ground' it with multiple vias. And just use solder mask to open parts to get the same effect.
Change some 'stars' to vias (not tented!)

Sniper2 , 11-12-2025, 05:46 AM

Did you check hdmi chip power up sequence?

Sniper2 , 11-12-2025, 05:47 AM

Also how does vivado signal integrity thinking work?

HasanTheSyrian_ , 11-12-2025, 07:01 PM

what do you mean? there is no reset for ftdi the pin is just pulled up. are you saying its somewhat common to have to reset and that i should have an ftdi reset?

HasanTheSyrian_ , 11-12-2025, 07:02 PM

vbus is managed by these ics

HasanTheSyrian_ , 11-12-2025, 07:03 PM

yes hdmi and ftdi turn on after vdd_3v3 but they turn on at the same time

Sniper2 , 11-12-2025, 08:12 PM

TLDR u can reset the FPGA via buton but the chips are not reset

Sniper2 , 11-12-2025, 08:12 PM

to reset them u need to unpower the PCB

HasanTheSyrian_ , 11-12-2025, 08:13 PM

yes i know

HasanTheSyrian_ , 11-12-2025, 08:13 PM

the reset in my pcb is for the fpga

Sniper2 , 11-12-2025, 08:13 PM

AGAIN Qdrive was sort of impliing to also use the FPGA reset to reset them if need be and maybe leave a 0ohm in the middle

Sniper2 , 11-12-2025, 08:14 PM

Also how did you get lower signal noise if you split the HDMI interface?

HasanTheSyrian_ , 11-12-2025, 08:16 PM

lower noise inside the fpga

Sniper2 , 11-12-2025, 08:19 PM

is is each HDMI in its own bank or how did you split more exactli, i dont understand well how and why

HasanTheSyrian_ , 11-12-2025, 08:20 PM

each hdmi has its own bank, look for simultaneously switching noise, ssn

Sniper2 , 11-12-2025, 08:40 PM

ok that makes sense

Sniper2 , 11-12-2025, 08:40 PM

i understood that u took 1 hdmi and split it for some esotheric reason

QDrives , 11-12-2025, 11:36 PM

There is a reset. I just notify you about issues I have seen with the FT230XS device.

QDrives , 11-12-2025, 11:38 PM

I have seen them, that is why I ask: is you USB bus a power input or power output?
The FT2232 is a peripheral device, so the USB should be a power input and not a power output as you get with the SP2526.

HasanTheSyrian_ , 11-13-2025, 08:38 AM

Im saying there is no FTDI reset on my board. The FTDI reset pin is tied high. Are you saying its more convenient to have a reset? If so I can just add a button next to it

HasanTheSyrian_ , 11-13-2025, 08:39 AM

The board supplies VBUS. The datasheet shows different configurations, one self powered and one VBUS powered

HasanTheSyrian_ , 11-13-2025, 08:41 AM

HasanTheSyrian_ , 11-13-2025, 08:41 AM

this is what im using v

HasanTheSyrian_ , 11-13-2025, 08:42 AM

i used multiple schematics as reference too

HasanTheSyrian_ , 11-13-2025, 08:42 AM

there was one IEEE paper that reversed the digilent programmer that i also used

HasanTheSyrian_ , 11-13-2025, 08:42 AM

(i lost access to ieee bc i graduated 😢 )

HasanTheSyrian_ , 11-13-2025, 08:43 AM

and as far as i remember i even used the same LDO in ftdi's reference schematics

HasanTheSyrian_ , 11-13-2025, 09:43 AM

actually it seems that i have forgotten the two resistors on the right there

HasanTheSyrian_ , 11-13-2025, 09:43 AM

schematics that i copied from use vbus power so ill have to double check that

HasanTheSyrian_ , 11-13-2025, 09:44 AM

yep the pynq z2 board uses self powered and it has them

QDrives , 11-13-2025, 10:37 PM

You have it similar to the datasheet, so you should be ok.

QDrives , 11-13-2025, 10:37 PM

No, for peripheral mode you do **not** supply Vbus. Vbus is supplied by the host.